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SkyNet
3.0
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Go to the source code of this file.
Data Structures | |
| union | UU16 |
| struct | si446x_reply_GENERIC_map |
| struct | si446x_reply_PART_INFO_map |
| struct | si446x_reply_FUNC_INFO_map |
| struct | si446x_reply_GET_PROPERTY_map |
| struct | si446x_reply_GPIO_PIN_CFG_map |
| struct | si446x_reply_GET_ADC_READING_map |
| struct | si446x_reply_FIFO_INFO_map |
| struct | si446x_reply_PACKET_INFO_map |
| struct | si446x_reply_IRCAL_map |
| struct | si446x_reply_GET_INT_STATUS_map |
| struct | si446x_reply_GET_PH_STATUS_map |
| struct | si446x_reply_GET_MODEM_STATUS_map |
| struct | si446x_reply_GET_CHIP_STATUS_map |
| struct | si446x_reply_REQUEST_DEVICE_STATE_map |
| struct | si446x_reply_READ_CMD_BUFF_map |
| struct | si446x_reply_FRR_A_READ_map |
| struct | si446x_reply_FRR_B_READ_map |
| struct | si446x_reply_FRR_C_READ_map |
| struct | si446x_reply_FRR_D_READ_map |
| union | si446x_cmd_reply_union |
Typedefs | |
| typedef uint8_t | U8 |
| typedef uint16_t | U16 |
| typedef uint32_t | U32 |
| typedef int8_t | S8 |
| typedef int16_t | S16 |
| typedef uint32_t | S32 |
| typedef union UU16 | UU16 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_AGC_OVERRIDE_INDEX 1 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_AGC_OVERRIDE_LSB 0 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_AGC_OVERRIDE_MASK 0xFF |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_AGC_OVERRIDE_MSB 7 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_AGC_OVERRIDE_SIZE 8 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_AGC_OVERRIDE_TYPE bitfield |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_AGC_OVERRIDE_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_LNA_AGC_BIT 0x08 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_LNA_AGC_INDEX 1 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_LNA_AGC_is_true (cmd.arg.RAW[1]&0x8) |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_LNA_AGC_LSB 3 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_LNA_AGC_MASK 0x08 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_LNA_AGC_MSB 3 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_LNA_AGC_SIZE 1 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_LNA_AGC_TYPE bitfield |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_LNA_AGC_value (((cmd.arg.RAW[1]&0x8))>>3) |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_PGA_AGC_BIT 0x80 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_PGA_AGC_INDEX 1 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_PGA_AGC_is_true (cmd.arg.RAW[1]&0x80) |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_PGA_AGC_LSB 7 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_PGA_AGC_MASK 0x80 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_PGA_AGC_MSB 7 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_PGA_AGC_SIZE 1 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_PGA_AGC_TYPE bitfield |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_DIS_PGA_AGC_value (((cmd.arg.RAW[1]&0x80))>>7) |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_LNA_GAIN_CFG_INDEX 1 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_LNA_GAIN_CFG_LSB 0 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_LNA_GAIN_CFG_MASK 0x07 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_LNA_GAIN_CFG_MSB 2 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_LNA_GAIN_CFG_SIZE 3 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_LNA_GAIN_CFG_TYPE bitfield |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_LNA_GAIN_CFG_value (((cmd.arg.RAW[1]&0x7))) |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_PGA_GAIN_CFG_INDEX 1 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_PGA_GAIN_CFG_LSB 4 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_PGA_GAIN_CFG_MASK 0x70 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_PGA_GAIN_CFG_MSB 6 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_PGA_GAIN_CFG_SIZE 3 |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_PGA_GAIN_CFG_TYPE bitfield |
| #define SI446X_CMD_AGC_OVERRIDE_ARG_PGA_GAIN_CFG_value (((cmd.arg.RAW[1]&0x70))>>4) |
| #define SI446X_CMD_ARG_COUNT_AGC_OVERRIDE 2 |
| #define SI446X_CMD_ARG_COUNT_CHANGE_STATE 2 |
| #define SI446X_CMD_ARG_COUNT_FIFO_INFO 2 |
| #define SI446X_CMD_ARG_COUNT_FRR_A_READ 1 |
| #define SI446X_CMD_ARG_COUNT_FRR_B_READ 1 |
| #define SI446X_CMD_ARG_COUNT_FRR_C_READ 1 |
| #define SI446X_CMD_ARG_COUNT_FRR_D_READ 1 |
| #define SI446X_CMD_ARG_COUNT_FUNC_INFO 1 |
| #define SI446X_CMD_ARG_COUNT_GET_ADC_READING 3 |
| #define SI446X_CMD_ARG_COUNT_GET_CHIP_STATUS 1 |
| #define SI446X_CMD_ARG_COUNT_GET_INT_STATUS 4 |
| #define SI446X_CMD_ARG_COUNT_GET_MODEM_STATUS 1 |
| #define SI446X_CMD_ARG_COUNT_GET_PH_STATUS 1 |
| #define SI446X_CMD_ARG_COUNT_GET_PROPERTY 4 |
| #define SI446X_CMD_ARG_COUNT_GPIO_PIN_CFG 8 |
| #define SI446X_CMD_ARG_COUNT_IRCAL 5 |
| #define SI446X_CMD_ARG_COUNT_NOP 1 |
| #define SI446X_CMD_ARG_COUNT_PACKET_INFO 6 |
| #define SI446X_CMD_ARG_COUNT_PART_INFO 1 |
| #define SI446X_CMD_ARG_COUNT_POWER_UP 7 |
| #define SI446X_CMD_ARG_COUNT_PROTOCOL_CFG 2 |
| #define SI446X_CMD_ARG_COUNT_READ_CMD_BUFF 1 |
| #define SI446X_CMD_ARG_COUNT_READ_RX_FIFO 1 |
| #define SI446X_CMD_ARG_COUNT_REQUEST_DEVICE_STATE 1 |
| #define SI446X_CMD_ARG_COUNT_RX_HOP 7 |
| #define SI446X_CMD_ARG_COUNT_SET_PROPERTY 16 |
| #define SI446X_CMD_ARG_COUNT_START_MFSK 4 |
| #define SI446X_CMD_ARG_COUNT_START_RX 8 |
| #define SI446X_CMD_ARG_COUNT_START_TX 6 |
| #define SI446X_CMD_ARG_COUNT_WRITE_TX_FIFO 2 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_NOCHANGE 0 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_READY 3 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_READY2 4 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_RX 8 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_RX_TUNE 6 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_SLEEP 1 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_SPI_ACTIVE 2 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_TX 7 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_ENUM_TX_TUNE 5 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_INDEX 1 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_LSB 0 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_MASK 0x0F |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_MSB 3 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_SIZE 4 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_TYPE bitfield |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEW_STATE_value (((cmd.arg.RAW[1]&0xF))) |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEXT_STATE1_INDEX 1 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEXT_STATE1_LSB 0 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEXT_STATE1_MASK 0xFF |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEXT_STATE1_MSB 7 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEXT_STATE1_SIZE 8 |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEXT_STATE1_TYPE bitfield |
| #define SI446X_CMD_CHANGE_STATE_ARG_NEXT_STATE1_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_FIFO_INFO_ARG_FIFO_INDEX 1 |
| #define SI446X_CMD_FIFO_INFO_ARG_FIFO_LSB 0 |
| #define SI446X_CMD_FIFO_INFO_ARG_FIFO_MASK 0xFF |
| #define SI446X_CMD_FIFO_INFO_ARG_FIFO_MSB 7 |
| #define SI446X_CMD_FIFO_INFO_ARG_FIFO_SIZE 8 |
| #define SI446X_CMD_FIFO_INFO_ARG_FIFO_TYPE bitfield |
| #define SI446X_CMD_FIFO_INFO_ARG_FIFO_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_FIFO_INFO_ARG_RX_BIT 0x02 |
| #define SI446X_CMD_FIFO_INFO_ARG_RX_ENUM_FALSE 0 |
| #define SI446X_CMD_FIFO_INFO_ARG_RX_ENUM_TRUE 1 |
| #define SI446X_CMD_FIFO_INFO_ARG_RX_INDEX 1 |
| #define SI446X_CMD_FIFO_INFO_ARG_RX_is_true (cmd.arg.RAW[1]&0x2) |
| #define SI446X_CMD_FIFO_INFO_ARG_RX_LSB 1 |
| #define SI446X_CMD_FIFO_INFO_ARG_RX_MASK 0x02 |
| #define SI446X_CMD_FIFO_INFO_ARG_RX_MSB 1 |
| #define SI446X_CMD_FIFO_INFO_ARG_RX_SIZE 1 |
| #define SI446X_CMD_FIFO_INFO_ARG_RX_TYPE bitfield |
| #define SI446X_CMD_FIFO_INFO_ARG_RX_value (((cmd.arg.RAW[1]&0x2))>>1) |
| #define SI446X_CMD_FIFO_INFO_ARG_TX_BIT 0x01 |
| #define SI446X_CMD_FIFO_INFO_ARG_TX_ENUM_FALSE 0 |
| #define SI446X_CMD_FIFO_INFO_ARG_TX_ENUM_TRUE 1 |
| #define SI446X_CMD_FIFO_INFO_ARG_TX_INDEX 1 |
| #define SI446X_CMD_FIFO_INFO_ARG_TX_is_true (cmd.arg.RAW[1]&0x1) |
| #define SI446X_CMD_FIFO_INFO_ARG_TX_LSB 0 |
| #define SI446X_CMD_FIFO_INFO_ARG_TX_MASK 0x01 |
| #define SI446X_CMD_FIFO_INFO_ARG_TX_MSB 0 |
| #define SI446X_CMD_FIFO_INFO_ARG_TX_SIZE 1 |
| #define SI446X_CMD_FIFO_INFO_ARG_TX_TYPE bitfield |
| #define SI446X_CMD_FIFO_INFO_ARG_TX_value (((cmd.arg.RAW[1]&0x1))) |
| #define SI446X_CMD_FIFO_INFO_REP_RX_FIFO_COUNT_INDEX 1 |
| #define SI446X_CMD_FIFO_INFO_REP_RX_FIFO_COUNT_LSB 0 |
| #define SI446X_CMD_FIFO_INFO_REP_RX_FIFO_COUNT_MASK 0xFF |
| #define SI446X_CMD_FIFO_INFO_REP_RX_FIFO_COUNT_MSB 7 |
| #define SI446X_CMD_FIFO_INFO_REP_RX_FIFO_COUNT_SIZE 8 |
| #define SI446X_CMD_FIFO_INFO_REP_RX_FIFO_COUNT_TYPE u8 |
| #define SI446X_CMD_FIFO_INFO_REP_TX_FIFO_SPACE_INDEX 2 |
| #define SI446X_CMD_FIFO_INFO_REP_TX_FIFO_SPACE_LSB 0 |
| #define SI446X_CMD_FIFO_INFO_REP_TX_FIFO_SPACE_MASK 0xFF |
| #define SI446X_CMD_FIFO_INFO_REP_TX_FIFO_SPACE_MSB 7 |
| #define SI446X_CMD_FIFO_INFO_REP_TX_FIFO_SPACE_SIZE 8 |
| #define SI446X_CMD_FIFO_INFO_REP_TX_FIFO_SPACE_TYPE u8 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_B_VALUE_INDEX 1 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_B_VALUE_LSB 0 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_B_VALUE_MASK 0xFF |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_B_VALUE_MSB 7 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_B_VALUE_SIZE 8 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_B_VALUE_TYPE u8 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_C_VALUE_INDEX 2 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_C_VALUE_LSB 0 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_C_VALUE_MASK 0xFF |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_C_VALUE_MSB 7 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_C_VALUE_SIZE 8 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_C_VALUE_TYPE u8 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_D_VALUE_INDEX 3 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_D_VALUE_LSB 0 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_D_VALUE_MASK 0xFF |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_D_VALUE_MSB 7 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_D_VALUE_SIZE 8 |
| #define SI446X_CMD_FRR_A_READ_REP_FRR_D_VALUE_TYPE u8 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_A_VALUE_INDEX 3 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_A_VALUE_LSB 0 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_A_VALUE_MASK 0xFF |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_A_VALUE_MSB 7 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_A_VALUE_SIZE 8 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_A_VALUE_TYPE u8 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_C_VALUE_INDEX 1 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_C_VALUE_LSB 0 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_C_VALUE_MASK 0xFF |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_C_VALUE_MSB 7 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_C_VALUE_SIZE 8 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_C_VALUE_TYPE u8 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_D_VALUE_INDEX 2 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_D_VALUE_LSB 0 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_D_VALUE_MASK 0xFF |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_D_VALUE_MSB 7 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_D_VALUE_SIZE 8 |
| #define SI446X_CMD_FRR_B_READ_REP_FRR_D_VALUE_TYPE u8 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_A_VALUE_INDEX 2 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_A_VALUE_LSB 0 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_A_VALUE_MASK 0xFF |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_A_VALUE_MSB 7 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_A_VALUE_SIZE 8 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_A_VALUE_TYPE u8 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_B_VALUE_INDEX 3 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_B_VALUE_LSB 0 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_B_VALUE_MASK 0xFF |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_B_VALUE_MSB 7 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_B_VALUE_SIZE 8 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_B_VALUE_TYPE u8 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_D_VALUE_INDEX 1 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_D_VALUE_LSB 0 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_D_VALUE_MASK 0xFF |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_D_VALUE_MSB 7 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_D_VALUE_SIZE 8 |
| #define SI446X_CMD_FRR_C_READ_REP_FRR_D_VALUE_TYPE u8 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_A_VALUE_INDEX 1 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_A_VALUE_LSB 0 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_A_VALUE_MASK 0xFF |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_A_VALUE_MSB 7 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_A_VALUE_SIZE 8 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_A_VALUE_TYPE u8 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_B_VALUE_INDEX 2 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_B_VALUE_LSB 0 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_B_VALUE_MASK 0xFF |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_B_VALUE_MSB 7 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_B_VALUE_SIZE 8 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_B_VALUE_TYPE u8 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_C_VALUE_INDEX 3 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_C_VALUE_LSB 0 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_C_VALUE_MASK 0xFF |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_C_VALUE_MSB 7 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_C_VALUE_SIZE 8 |
| #define SI446X_CMD_FRR_D_READ_REP_FRR_C_VALUE_TYPE u8 |
| #define SI446X_CMD_FUNC_INFO_REP_FUNC_ENUM_BOOT 0 |
| #define SI446X_CMD_FUNC_INFO_REP_FUNC_ENUM_MAIN 1 |
| #define SI446X_CMD_FUNC_INFO_REP_FUNC_INDEX 6 |
| #define SI446X_CMD_FUNC_INFO_REP_FUNC_LSB 0 |
| #define SI446X_CMD_FUNC_INFO_REP_FUNC_MASK 0xFF |
| #define SI446X_CMD_FUNC_INFO_REP_FUNC_MSB 7 |
| #define SI446X_CMD_FUNC_INFO_REP_FUNC_SIZE 8 |
| #define SI446X_CMD_FUNC_INFO_REP_FUNC_TYPE u8 |
| #define SI446X_CMD_FUNC_INFO_REP_PATCH_INDEX 4 |
| #define SI446X_CMD_FUNC_INFO_REP_PATCH_LSB 0 |
| #define SI446X_CMD_FUNC_INFO_REP_PATCH_MASK 0xFFFF |
| #define SI446X_CMD_FUNC_INFO_REP_PATCH_MSB 15 |
| #define SI446X_CMD_FUNC_INFO_REP_PATCH_SIZE 16 |
| #define SI446X_CMD_FUNC_INFO_REP_PATCH_TYPE u16 |
| #define SI446X_CMD_FUNC_INFO_REP_REVBRANCH_INDEX 2 |
| #define SI446X_CMD_FUNC_INFO_REP_REVBRANCH_LSB 0 |
| #define SI446X_CMD_FUNC_INFO_REP_REVBRANCH_MASK 0xFF |
| #define SI446X_CMD_FUNC_INFO_REP_REVBRANCH_MAX 255 |
| #define SI446X_CMD_FUNC_INFO_REP_REVBRANCH_MIN 0 |
| #define SI446X_CMD_FUNC_INFO_REP_REVBRANCH_MSB 7 |
| #define SI446X_CMD_FUNC_INFO_REP_REVBRANCH_SIZE 8 |
| #define SI446X_CMD_FUNC_INFO_REP_REVBRANCH_TYPE u8 |
| #define SI446X_CMD_FUNC_INFO_REP_REVEXT_INDEX 1 |
| #define SI446X_CMD_FUNC_INFO_REP_REVEXT_LSB 0 |
| #define SI446X_CMD_FUNC_INFO_REP_REVEXT_MASK 0xFF |
| #define SI446X_CMD_FUNC_INFO_REP_REVEXT_MAX 255 |
| #define SI446X_CMD_FUNC_INFO_REP_REVEXT_MIN 0 |
| #define SI446X_CMD_FUNC_INFO_REP_REVEXT_MSB 7 |
| #define SI446X_CMD_FUNC_INFO_REP_REVEXT_SIZE 8 |
| #define SI446X_CMD_FUNC_INFO_REP_REVEXT_TYPE u8 |
| #define SI446X_CMD_FUNC_INFO_REP_REVINT_INDEX 3 |
| #define SI446X_CMD_FUNC_INFO_REP_REVINT_LSB 0 |
| #define SI446X_CMD_FUNC_INFO_REP_REVINT_MASK 0xFF |
| #define SI446X_CMD_FUNC_INFO_REP_REVINT_MAX 255 |
| #define SI446X_CMD_FUNC_INFO_REP_REVINT_MIN 0 |
| #define SI446X_CMD_FUNC_INFO_REP_REVINT_MSB 7 |
| #define SI446X_CMD_FUNC_INFO_REP_REVINT_SIZE 8 |
| #define SI446X_CMD_FUNC_INFO_REP_REVINT_TYPE u8 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_CFG_INDEX 2 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_CFG_LSB 0 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_CFG_MASK 0xFF |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_CFG_MSB 7 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_CFG_SIZE 8 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_CFG_TYPE bitfield |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_CFG_value (((cmd.arg.RAW[2]))) |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_EN_INDEX 1 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_EN_LSB 0 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_EN_MASK 0xFF |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_EN_MSB 7 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_EN_SIZE 8 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_EN_TYPE bitfield |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_EN_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_EN_BIT 0x04 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_EN_INDEX 1 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_EN_is_true (cmd.arg.RAW[1]&0x4) |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_EN_LSB 2 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_EN_MASK 0x04 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_EN_MSB 2 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_EN_SIZE 1 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_EN_TYPE bitfield |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_EN_value (((cmd.arg.RAW[1]&0x4))>>2) |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_PIN_INDEX 1 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_PIN_LSB 0 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_PIN_MASK 0x03 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_PIN_MSB 1 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_PIN_SIZE 2 |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_PIN_TYPE bitfield |
| #define SI446X_CMD_GET_ADC_READING_ARG_ADC_GPIO_PIN_value (((cmd.arg.RAW[1]&0x3))) |
| #define SI446X_CMD_GET_ADC_READING_ARG_BATTERY_VOLTAGE_EN_BIT 0x08 |
| #define SI446X_CMD_GET_ADC_READING_ARG_BATTERY_VOLTAGE_EN_INDEX 1 |
| #define SI446X_CMD_GET_ADC_READING_ARG_BATTERY_VOLTAGE_EN_is_true (cmd.arg.RAW[1]&0x8) |
| #define SI446X_CMD_GET_ADC_READING_ARG_BATTERY_VOLTAGE_EN_LSB 3 |
| #define SI446X_CMD_GET_ADC_READING_ARG_BATTERY_VOLTAGE_EN_MASK 0x08 |
| #define SI446X_CMD_GET_ADC_READING_ARG_BATTERY_VOLTAGE_EN_MSB 3 |
| #define SI446X_CMD_GET_ADC_READING_ARG_BATTERY_VOLTAGE_EN_SIZE 1 |
| #define SI446X_CMD_GET_ADC_READING_ARG_BATTERY_VOLTAGE_EN_TYPE bitfield |
| #define SI446X_CMD_GET_ADC_READING_ARG_BATTERY_VOLTAGE_EN_value (((cmd.arg.RAW[1]&0x8))>>3) |
| #define SI446X_CMD_GET_ADC_READING_ARG_GPIO_ATT_ENUM_0P8 0x0 |
| #define SI446X_CMD_GET_ADC_READING_ARG_GPIO_ATT_ENUM_1P6 0x4 |
| #define SI446X_CMD_GET_ADC_READING_ARG_GPIO_ATT_ENUM_2P4 0x8 |
| #define SI446X_CMD_GET_ADC_READING_ARG_GPIO_ATT_ENUM_3P2 0xC |
| #define SI446X_CMD_GET_ADC_READING_ARG_GPIO_ATT_ENUM_3P6 0x9 |
| #define SI446X_CMD_GET_ADC_READING_ARG_GPIO_ATT_INDEX 2 |
| #define SI446X_CMD_GET_ADC_READING_ARG_GPIO_ATT_LSB 0 |
| #define SI446X_CMD_GET_ADC_READING_ARG_GPIO_ATT_MASK 0x0F |
| #define SI446X_CMD_GET_ADC_READING_ARG_GPIO_ATT_MSB 3 |
| #define SI446X_CMD_GET_ADC_READING_ARG_GPIO_ATT_SIZE 4 |
| #define SI446X_CMD_GET_ADC_READING_ARG_GPIO_ATT_TYPE bitfield |
| #define SI446X_CMD_GET_ADC_READING_ARG_GPIO_ATT_value (((cmd.arg.RAW[2]&0xF))) |
| #define SI446X_CMD_GET_ADC_READING_ARG_TEMPERATURE_EN_BIT 0x10 |
| #define SI446X_CMD_GET_ADC_READING_ARG_TEMPERATURE_EN_INDEX 1 |
| #define SI446X_CMD_GET_ADC_READING_ARG_TEMPERATURE_EN_is_true (cmd.arg.RAW[1]&0x10) |
| #define SI446X_CMD_GET_ADC_READING_ARG_TEMPERATURE_EN_LSB 4 |
| #define SI446X_CMD_GET_ADC_READING_ARG_TEMPERATURE_EN_MASK 0x10 |
| #define SI446X_CMD_GET_ADC_READING_ARG_TEMPERATURE_EN_MSB 4 |
| #define SI446X_CMD_GET_ADC_READING_ARG_TEMPERATURE_EN_SIZE 1 |
| #define SI446X_CMD_GET_ADC_READING_ARG_TEMPERATURE_EN_TYPE bitfield |
| #define SI446X_CMD_GET_ADC_READING_ARG_TEMPERATURE_EN_value (((cmd.arg.RAW[1]&0x10))>>4) |
| #define SI446X_CMD_GET_ADC_READING_ARG_UDTIME_INDEX 2 |
| #define SI446X_CMD_GET_ADC_READING_ARG_UDTIME_LSB 4 |
| #define SI446X_CMD_GET_ADC_READING_ARG_UDTIME_MASK 0xF0 |
| #define SI446X_CMD_GET_ADC_READING_ARG_UDTIME_MSB 7 |
| #define SI446X_CMD_GET_ADC_READING_ARG_UDTIME_SIZE 4 |
| #define SI446X_CMD_GET_ADC_READING_ARG_UDTIME_TYPE bitfield |
| #define SI446X_CMD_GET_ADC_READING_ARG_UDTIME_value (((cmd.arg.RAW[2]&0xF0))>>4) |
| #define SI446X_CMD_GET_ADC_READING_REP_BATTERY_ADC_INDEX 3 |
| #define SI446X_CMD_GET_ADC_READING_REP_BATTERY_ADC_LSB 0 |
| #define SI446X_CMD_GET_ADC_READING_REP_BATTERY_ADC_MASK 0xFFFF |
| #define SI446X_CMD_GET_ADC_READING_REP_BATTERY_ADC_MSB 15 |
| #define SI446X_CMD_GET_ADC_READING_REP_BATTERY_ADC_SIZE 16 |
| #define SI446X_CMD_GET_ADC_READING_REP_BATTERY_ADC_TYPE u16 |
| #define SI446X_CMD_GET_ADC_READING_REP_GPIO_ADC_INDEX 1 |
| #define SI446X_CMD_GET_ADC_READING_REP_GPIO_ADC_LSB 0 |
| #define SI446X_CMD_GET_ADC_READING_REP_GPIO_ADC_MASK 0xFFFF |
| #define SI446X_CMD_GET_ADC_READING_REP_GPIO_ADC_MSB 15 |
| #define SI446X_CMD_GET_ADC_READING_REP_GPIO_ADC_SIZE 16 |
| #define SI446X_CMD_GET_ADC_READING_REP_GPIO_ADC_TYPE u16 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_ADC_INDEX 5 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_ADC_LSB 0 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_ADC_MASK 0xFFFF |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_ADC_MSB 15 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_ADC_SIZE 16 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_ADC_TYPE u16 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_INTERCEPT_INDEX 8 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_INTERCEPT_LSB 0 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_INTERCEPT_MASK 0xFF |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_INTERCEPT_MSB 7 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_INTERCEPT_SIZE 8 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_INTERCEPT_TYPE u8 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_SLOPE_INDEX 7 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_SLOPE_LSB 0 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_SLOPE_MASK 0xFF |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_SLOPE_MSB 7 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_SLOPE_SIZE 8 |
| #define SI446X_CMD_GET_ADC_READING_REP_TEMP_SLOPE_TYPE u8 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CAL_BIT 0x40 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CAL_INDEX 2 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CAL_LSB 6 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CAL_MASK 0x40 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CAL_MSB 6 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CAL_PEND_BIT 0x40 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CAL_PEND_INDEX 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CAL_PEND_LSB 6 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CAL_PEND_MASK 0x40 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CAL_PEND_MSB 6 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CAL_PEND_SIZE 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CAL_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CAL_SIZE 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CAL_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_PEND_INDEX 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_PEND_LSB 0 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_PEND_MASK 0xFF |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_PEND_MSB 7 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_PEND_SIZE 8 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_READY_BIT 0x04 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_READY_INDEX 2 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_READY_LSB 2 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_READY_MASK 0x04 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_READY_MSB 2 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_READY_PEND_BIT 0x04 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_READY_PEND_INDEX 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_READY_PEND_LSB 2 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_READY_PEND_MASK 0x04 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_READY_PEND_MSB 2 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_READY_PEND_SIZE 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_READY_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_READY_SIZE 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_READY_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_STATUS_INDEX 2 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_STATUS_LSB 0 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_STATUS_MASK 0xFF |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_STATUS_MSB 7 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_STATUS_SIZE 8 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CHIP_STATUS_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_BAD_ARG 0x11 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_BAD_BOOTMODE 0x31 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_BAD_COMMAND 0x10 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_BAD_NVM 0x20 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_BAD_PATCH 0x30 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_BAD_PROPERTY 0x40 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_COMMAND_BUSY 0x12 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_ENUM_CMD_ERROR_NONE 0x00 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_INDEX 3 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_LSB 0 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_MASK 0xFF |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_MSB 7 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_SIZE 8 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERR_STATUS_TYPE u8 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_BIT 0x08 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_INDEX 2 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_LSB 3 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_MASK 0x08 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_MSB 3 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_BIT 0x08 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_INDEX 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_LSB 3 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_MASK 0x08 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_MSB 3 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_SIZE 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_SIZE 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_CMD_ERROR_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_BIT 0x20 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_INDEX 2 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_LSB 5 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_MASK 0x20 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_MSB 5 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_BIT 0x20 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_INDEX 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_LSB 5 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_MASK 0x20 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_MSB 5 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_SIZE 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_SIZE 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_LOW_BATT_BIT 0x02 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_LOW_BATT_INDEX 2 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_LOW_BATT_LSB 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_LOW_BATT_MASK 0x02 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_LOW_BATT_MSB 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_LOW_BATT_PEND_BIT 0x02 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_LOW_BATT_PEND_INDEX 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_LOW_BATT_PEND_LSB 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_LOW_BATT_PEND_MASK 0x02 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_LOW_BATT_PEND_MSB 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_LOW_BATT_PEND_SIZE 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_LOW_BATT_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_LOW_BATT_SIZE 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_LOW_BATT_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_BIT 0x10 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_INDEX 2 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_LSB 4 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_MASK 0x10 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_MSB 4 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_PEND_BIT 0x10 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_PEND_INDEX 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_PEND_LSB 4 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_PEND_MASK 0x10 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_PEND_MSB 4 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_PEND_SIZE 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_SIZE 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_STATE_CHANGE_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_WUT_BIT 0x01 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_WUT_INDEX 2 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_WUT_LSB 0 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_WUT_MASK 0x01 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_WUT_MSB 0 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_WUT_PEND_BIT 0x01 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_WUT_PEND_INDEX 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_WUT_PEND_LSB 0 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_WUT_PEND_MASK 0x01 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_WUT_PEND_MSB 0 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_WUT_PEND_SIZE 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_WUT_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_WUT_SIZE 1 |
| #define SI446X_CMD_GET_CHIP_STATUS_REP_WUT_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_BIT 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_is_true (cmd.arg.RAW[3]&0x40) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_LSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_MASK 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_MSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CAL_PEND_CLR_value (((cmd.arg.RAW[3]&0x40))>>6) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_CLR_PEND_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_CLR_PEND_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_CLR_PEND_MASK 0xFF |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_CLR_PEND_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_CLR_PEND_SIZE 8 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_CLR_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_CLR_PEND_value (((cmd.arg.RAW[3]))) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_BIT 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_is_true (cmd.arg.RAW[3]&0x4) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_LSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_MASK 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_MSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CHIP_READY_PEND_CLR_value (((cmd.arg.RAW[3]&0x4))>>2) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_BIT 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_is_true (cmd.arg.RAW[3]&0x8) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_LSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_MASK 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_MSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CMD_ERROR_PEND_CLR_value (((cmd.arg.RAW[3]&0x8))>>3) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_BIT 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_INDEX 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_is_true (cmd.arg.RAW[1]&0x8) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_LSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_MASK 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_MSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_CRC_ERROR_PEND_CLR_value (((cmd.arg.RAW[1]&0x8))>>3) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_BIT 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_is_true (cmd.arg.RAW[3]&0x20) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_LSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_MASK 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_MSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_CLR_value (((cmd.arg.RAW[3]&0x20))>>5) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MATCH_PEND_CLR_BIT 0x80 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MATCH_PEND_CLR_INDEX 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MATCH_PEND_CLR_is_true (cmd.arg.RAW[1]&0x80) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MATCH_PEND_CLR_LSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MATCH_PEND_CLR_MASK 0x80 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MATCH_PEND_CLR_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MATCH_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MATCH_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MATCH_PEND_CLR_value (((cmd.arg.RAW[1]&0x80))>>7) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MISS_PEND_CLR_BIT 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MISS_PEND_CLR_INDEX 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MISS_PEND_CLR_is_true (cmd.arg.RAW[1]&0x40) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MISS_PEND_CLR_LSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MISS_PEND_CLR_MASK 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MISS_PEND_CLR_MSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MISS_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MISS_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_FILTER_MISS_PEND_CLR_value (((cmd.arg.RAW[1]&0x40))>>6) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_BIT 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_INDEX 2 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_is_true (cmd.arg.RAW[2]&0x4) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_LSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_MASK 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_MSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_PREAMBLE_PEND_CLR_value (((cmd.arg.RAW[2]&0x4))>>2) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_BIT 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_INDEX 2 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_is_true (cmd.arg.RAW[2]&0x20) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_LSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_MASK 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_MSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_INVALID_SYNC_PEND_CLR_value (((cmd.arg.RAW[2]&0x20))>>5) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_LOW_BATT_PEND_CLR_BIT 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_LOW_BATT_PEND_CLR_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_LOW_BATT_PEND_CLR_is_true (cmd.arg.RAW[3]&0x2) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_LOW_BATT_PEND_CLR_LSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_LOW_BATT_PEND_CLR_MASK 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_LOW_BATT_PEND_CLR_MSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_LOW_BATT_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_LOW_BATT_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_LOW_BATT_PEND_CLR_value (((cmd.arg.RAW[3]&0x2))>>1) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_MODEM_CLR_PEND_INDEX 2 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_MODEM_CLR_PEND_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_MODEM_CLR_PEND_MASK 0xFF |
| #define SI446X_CMD_GET_INT_STATUS_ARG_MODEM_CLR_PEND_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_MODEM_CLR_PEND_SIZE 8 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_MODEM_CLR_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_MODEM_CLR_PEND_value (((cmd.arg.RAW[2]))) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_BIT 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_INDEX 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_is_true (cmd.arg.RAW[1]&0x10) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_LSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_MASK 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_MSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_RX_PEND_CLR_value (((cmd.arg.RAW[1]&0x10))>>4) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_BIT 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_INDEX 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_is_true (cmd.arg.RAW[1]&0x20) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_LSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_MASK 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_MSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PACKET_SENT_PEND_CLR_value (((cmd.arg.RAW[1]&0x20))>>5) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PH_CLR_PEND_INDEX 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PH_CLR_PEND_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PH_CLR_PEND_MASK 0xFF |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PH_CLR_PEND_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PH_CLR_PEND_SIZE 8 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PH_CLR_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PH_CLR_PEND_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_BIT 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_INDEX 2 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_is_true (cmd.arg.RAW[2]&0x40) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_LSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_MASK 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_MSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_POSTAMBLE_DETECT_PEND_CLR_value (((cmd.arg.RAW[2]&0x40))>>6) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_BIT 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_INDEX 2 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_is_true (cmd.arg.RAW[2]&0x2) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_LSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_MASK 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_MSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_PREAMBLE_DETECT_PEND_CLR_value (((cmd.arg.RAW[2]&0x2))>>1) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_BIT 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_INDEX 2 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_is_true (cmd.arg.RAW[2]&0x10) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_LSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_MASK 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_MSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_JUMP_PEND_CLR_value (((cmd.arg.RAW[2]&0x10))>>4) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_LATCH_PEND_CLR_BIT 0x80 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_LATCH_PEND_CLR_INDEX 2 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_LATCH_PEND_CLR_is_true (cmd.arg.RAW[2]&0x80) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_LATCH_PEND_CLR_LSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_LATCH_PEND_CLR_MASK 0x80 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_LATCH_PEND_CLR_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_LATCH_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_LATCH_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_LATCH_PEND_CLR_value (((cmd.arg.RAW[2]&0x80))>>7) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_BIT 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_INDEX 2 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_is_true (cmd.arg.RAW[2]&0x8) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_LSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_MASK 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_MSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RSSI_PEND_CLR_value (((cmd.arg.RAW[2]&0x8))>>3) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_BIT 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_INDEX 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_is_true (cmd.arg.RAW[1]&0x1) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_MASK 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_MSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_RX_FIFO_ALMOST_FULL_PEND_CLR_value (((cmd.arg.RAW[1]&0x1))) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_BIT 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_is_true (cmd.arg.RAW[3]&0x10) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_LSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_MASK 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_MSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_STATE_CHANGE_PEND_CLR_value (((cmd.arg.RAW[3]&0x10))>>4) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_BIT 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_INDEX 2 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_is_true (cmd.arg.RAW[2]&0x1) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_MASK 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_MSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_SYNC_DETECT_PEND_CLR_value (((cmd.arg.RAW[2]&0x1))) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_BIT 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_INDEX 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_is_true (cmd.arg.RAW[1]&0x2) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_LSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_MASK 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_MSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_TX_FIFO_ALMOST_EMPTY_PEND_CLR_value (((cmd.arg.RAW[1]&0x2))>>1) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_WUT_PEND_CLR_BIT 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_WUT_PEND_CLR_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_WUT_PEND_CLR_is_true (cmd.arg.RAW[3]&0x1) |
| #define SI446X_CMD_GET_INT_STATUS_ARG_WUT_PEND_CLR_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_WUT_PEND_CLR_MASK 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_WUT_PEND_CLR_MSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_WUT_PEND_CLR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_ARG_WUT_PEND_CLR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_ARG_WUT_PEND_CLR_value (((cmd.arg.RAW[3]&0x1))) |
| #define SI446X_CMD_GET_INT_STATUS_REP_CAL_BIT 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CAL_INDEX 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CAL_LSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CAL_MASK 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CAL_MSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CAL_PEND_BIT 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CAL_PEND_INDEX 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CAL_PEND_LSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CAL_PEND_MASK 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CAL_PEND_MSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CAL_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CAL_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_CAL_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CAL_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_BIT 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_INDEX 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_LSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_MASK 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_MSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_PEND_BIT 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_PEND_INDEX 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_PEND_LSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_PEND_MASK 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_PEND_MSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_INT_STATUS_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_PEND_INDEX 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_PEND_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_PEND_MASK 0xFF |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_PEND_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_PEND_SIZE 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_READY_BIT 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_READY_INDEX 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_READY_LSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_READY_MASK 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_READY_MSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_READY_PEND_BIT 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_READY_PEND_INDEX 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_READY_PEND_LSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_READY_PEND_MASK 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_READY_PEND_MSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_READY_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_READY_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_READY_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_READY_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_STATUS_INDEX 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_STATUS_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_STATUS_MASK 0xFF |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_STATUS_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_STATUS_SIZE 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CHIP_STATUS_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_CMD_ERROR_BIT 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CMD_ERROR_INDEX 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CMD_ERROR_LSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CMD_ERROR_MASK 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CMD_ERROR_MSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CMD_ERROR_PEND_BIT 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CMD_ERROR_PEND_INDEX 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CMD_ERROR_PEND_LSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CMD_ERROR_PEND_MASK 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CMD_ERROR_PEND_MSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CMD_ERROR_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CMD_ERROR_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_CMD_ERROR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CMD_ERROR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_BIT 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_INDEX 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_LSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_MASK 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_MSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_PEND_BIT 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_PEND_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_PEND_LSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_PEND_MASK 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_PEND_MSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_CRC_ERROR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_BIT 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_INDEX 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_LSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_MASK 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_MSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_BIT 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_INDEX 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_LSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_MASK 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_MSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FIFO_UNDERFLOW_OVERFLOW_ERROR_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MATCH_BIT 0x80 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MATCH_INDEX 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MATCH_LSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MATCH_MASK 0x80 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MATCH_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MATCH_PEND_BIT 0x80 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MATCH_PEND_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MATCH_PEND_LSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MATCH_PEND_MASK 0x80 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MATCH_PEND_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MATCH_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MATCH_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MATCH_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MATCH_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MISS_BIT 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MISS_INDEX 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MISS_LSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MISS_MASK 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MISS_MSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MISS_PEND_BIT 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MISS_PEND_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MISS_PEND_LSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MISS_PEND_MASK 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MISS_PEND_MSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MISS_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MISS_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MISS_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_FILTER_MISS_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_INT_PEND_INDEX 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INT_PEND_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INT_PEND_MASK 0xFF |
| #define SI446X_CMD_GET_INT_STATUS_REP_INT_PEND_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INT_PEND_SIZE 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INT_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_INT_STATUS_INDEX 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INT_STATUS_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INT_STATUS_MASK 0xFF |
| #define SI446X_CMD_GET_INT_STATUS_REP_INT_STATUS_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INT_STATUS_SIZE 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INT_STATUS_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_BIT 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_INDEX 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_LSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_MASK 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_MSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_PEND_BIT 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_PEND_INDEX 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_PEND_LSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_PEND_MASK 0x04 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_PEND_MSB 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_PREAMBLE_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_SYNC_BIT 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_SYNC_INDEX 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_SYNC_LSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_SYNC_MASK 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_SYNC_MSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_SYNC_PEND_BIT 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_SYNC_PEND_INDEX 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_SYNC_PEND_LSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_SYNC_PEND_MASK 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_SYNC_PEND_MSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_SYNC_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_SYNC_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_SYNC_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_INVALID_SYNC_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_LOW_BATT_BIT 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_LOW_BATT_INDEX 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_LOW_BATT_LSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_LOW_BATT_MASK 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_LOW_BATT_MSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_LOW_BATT_PEND_BIT 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_LOW_BATT_PEND_INDEX 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_LOW_BATT_PEND_LSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_LOW_BATT_PEND_MASK 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_LOW_BATT_PEND_MSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_LOW_BATT_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_LOW_BATT_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_LOW_BATT_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_LOW_BATT_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_BIT 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_INDEX 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_LSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_MASK 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_MSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_PEND_BIT 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_PEND_INDEX 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_PEND_LSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_PEND_MASK 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_PEND_MSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_INT_STATUS_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_PEND_INDEX 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_PEND_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_PEND_MASK 0xFF |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_PEND_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_PEND_SIZE 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_STATUS_INDEX 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_STATUS_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_STATUS_MASK 0xFF |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_STATUS_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_STATUS_SIZE 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_MODEM_STATUS_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_BIT 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_INDEX 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_LSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_MASK 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_MSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_BIT 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_LSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_MASK 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_MSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_RX_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_SENT_BIT 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_SENT_INDEX 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_SENT_LSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_SENT_MASK 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_SENT_MSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_SENT_PEND_BIT 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_SENT_PEND_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_SENT_PEND_LSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_SENT_PEND_MASK 0x20 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_SENT_PEND_MSB 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_SENT_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_SENT_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_SENT_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PACKET_SENT_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_BIT 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_INDEX 2 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_MASK 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_MSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_PEND_BIT 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_PEND_INDEX 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_PEND_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_PEND_MASK 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_PEND_MSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_INT_STATUS_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_PEND_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_PEND_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_PEND_MASK 0xFF |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_PEND_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_PEND_SIZE 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_STATUS_INDEX 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_STATUS_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_STATUS_MASK 0xFF |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_STATUS_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_STATUS_SIZE 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PH_STATUS_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_BIT 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_INDEX 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_LSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_MASK 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_MSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_PEND_BIT 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_PEND_INDEX 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_PEND_LSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_PEND_MASK 0x40 |
| #define SI446X_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_PEND_MSB 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_POSTAMBLE_DETECT_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_BIT 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_INDEX 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_LSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_MASK 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_MSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_PEND_BIT 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_PEND_INDEX 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_PEND_LSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_PEND_MASK 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_PEND_MSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_PREAMBLE_DETECT_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_BIT 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_INDEX 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_JUMP_BIT 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_JUMP_INDEX 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_JUMP_LSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_JUMP_MASK 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_JUMP_MSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_JUMP_PEND_BIT 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_JUMP_PEND_INDEX 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_JUMP_PEND_LSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_JUMP_PEND_MASK 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_JUMP_PEND_MSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_JUMP_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_JUMP_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_JUMP_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_JUMP_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LATCH_BIT 0x80 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LATCH_INDEX 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LATCH_LSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LATCH_MASK 0x80 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LATCH_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LATCH_PEND_BIT 0x80 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LATCH_PEND_INDEX 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LATCH_PEND_LSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LATCH_PEND_MASK 0x80 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LATCH_PEND_MSB 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LATCH_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LATCH_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LATCH_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LATCH_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_LSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_MASK 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_MSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_PEND_BIT 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_PEND_INDEX 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_PEND_LSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_PEND_MASK 0x08 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_PEND_MSB 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RSSI_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_BIT 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_INDEX 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_MASK 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_MSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_BIT 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_MASK 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_MSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_RX_FIFO_ALMOST_FULL_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_STATE_CHANGE_BIT 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_REP_STATE_CHANGE_INDEX 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_STATE_CHANGE_LSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_STATE_CHANGE_MASK 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_REP_STATE_CHANGE_MSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_STATE_CHANGE_PEND_BIT 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_REP_STATE_CHANGE_PEND_INDEX 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_STATE_CHANGE_PEND_LSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_STATE_CHANGE_PEND_MASK 0x10 |
| #define SI446X_CMD_GET_INT_STATUS_REP_STATE_CHANGE_PEND_MSB 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_STATE_CHANGE_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_STATE_CHANGE_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_STATE_CHANGE_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_STATE_CHANGE_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_BIT 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_INDEX 6 |
| #define SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_MASK 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_MSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_BIT 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_INDEX 5 |
| #define SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_MASK 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_MSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_SYNC_DETECT_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_BIT 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_INDEX 4 |
| #define SI446X_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_LSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_MASK 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_MSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_BIT 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_INDEX 3 |
| #define SI446X_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_LSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_MASK 0x02 |
| #define SI446X_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_MSB 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_TX_FIFO_ALMOST_EMPTY_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_WUT_BIT 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_WUT_INDEX 8 |
| #define SI446X_CMD_GET_INT_STATUS_REP_WUT_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_WUT_MASK 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_WUT_MSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_WUT_PEND_BIT 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_WUT_PEND_INDEX 7 |
| #define SI446X_CMD_GET_INT_STATUS_REP_WUT_PEND_LSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_WUT_PEND_MASK 0x01 |
| #define SI446X_CMD_GET_INT_STATUS_REP_WUT_PEND_MSB 0 |
| #define SI446X_CMD_GET_INT_STATUS_REP_WUT_PEND_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_WUT_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_INT_STATUS_REP_WUT_SIZE 1 |
| #define SI446X_CMD_GET_INT_STATUS_REP_WUT_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_AFC_FREQ_OFFSET_INDEX 7 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_AFC_FREQ_OFFSET_LSB 0 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_AFC_FREQ_OFFSET_MASK 0xFFFF |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_AFC_FREQ_OFFSET_MSB 15 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_AFC_FREQ_OFFSET_SIZE 16 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_AFC_FREQ_OFFSET_TYPE u16 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_ANT1_RSSI_INDEX 5 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_ANT1_RSSI_LSB 0 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_ANT1_RSSI_MASK 0xFF |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_ANT1_RSSI_MSB 7 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_ANT1_RSSI_SIZE 8 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_ANT1_RSSI_TYPE u8 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_ANT2_RSSI_INDEX 6 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_ANT2_RSSI_LSB 0 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_ANT2_RSSI_MASK 0xFF |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_ANT2_RSSI_MSB 7 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_ANT2_RSSI_SIZE 8 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_ANT2_RSSI_TYPE u8 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_CURR_RSSI_INDEX 3 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_CURR_RSSI_LSB 0 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_CURR_RSSI_MASK 0xFF |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_CURR_RSSI_MSB 7 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_CURR_RSSI_SIZE 8 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_CURR_RSSI_TYPE u8 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_PREAMBLE_BIT 0x04 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_PREAMBLE_INDEX 2 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_PREAMBLE_LSB 2 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_PREAMBLE_MASK 0x04 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_PREAMBLE_MSB 2 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_PREAMBLE_PEND_BIT 0x04 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_PREAMBLE_PEND_INDEX 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_PREAMBLE_PEND_LSB 2 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_PREAMBLE_PEND_MASK 0x04 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_PREAMBLE_PEND_MSB 2 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_PREAMBLE_PEND_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_PREAMBLE_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_PREAMBLE_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_PREAMBLE_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_SYNC_BIT 0x20 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_SYNC_INDEX 2 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_SYNC_LSB 5 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_SYNC_MASK 0x20 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_SYNC_MSB 5 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_SYNC_PEND_BIT 0x20 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_SYNC_PEND_INDEX 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_SYNC_PEND_LSB 5 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_SYNC_PEND_MASK 0x20 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_SYNC_PEND_MSB 5 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_SYNC_PEND_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_SYNC_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_SYNC_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_INVALID_SYNC_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_LATCH_RSSI_INDEX 4 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_LATCH_RSSI_LSB 0 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_LATCH_RSSI_MASK 0xFF |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_LATCH_RSSI_MSB 7 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_LATCH_RSSI_SIZE 8 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_LATCH_RSSI_TYPE u8 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_MODEM_PEND_INDEX 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_MODEM_PEND_LSB 0 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_MODEM_PEND_MASK 0xFF |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_MODEM_PEND_MSB 7 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_MODEM_PEND_SIZE 8 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_MODEM_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_MODEM_STATUS_INDEX 2 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_MODEM_STATUS_LSB 0 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_MODEM_STATUS_MASK 0xFF |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_MODEM_STATUS_MSB 7 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_MODEM_STATUS_SIZE 8 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_MODEM_STATUS_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_POSTAMBLE_DETECT_BIT 0x40 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_POSTAMBLE_DETECT_INDEX 2 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_POSTAMBLE_DETECT_LSB 6 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_POSTAMBLE_DETECT_MASK 0x40 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_POSTAMBLE_DETECT_MSB 6 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_POSTAMBLE_DETECT_PEND_BIT 0x40 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_POSTAMBLE_DETECT_PEND_INDEX 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_POSTAMBLE_DETECT_PEND_LSB 6 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_POSTAMBLE_DETECT_PEND_MASK 0x40 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_POSTAMBLE_DETECT_PEND_MSB 6 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_POSTAMBLE_DETECT_PEND_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_POSTAMBLE_DETECT_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_POSTAMBLE_DETECT_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_POSTAMBLE_DETECT_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_PREAMBLE_DETECT_BIT 0x02 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_PREAMBLE_DETECT_INDEX 2 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_PREAMBLE_DETECT_LSB 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_PREAMBLE_DETECT_MASK 0x02 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_PREAMBLE_DETECT_MSB 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_PREAMBLE_DETECT_PEND_BIT 0x02 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_PREAMBLE_DETECT_PEND_INDEX 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_PREAMBLE_DETECT_PEND_LSB 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_PREAMBLE_DETECT_PEND_MASK 0x02 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_PREAMBLE_DETECT_PEND_MSB 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_PREAMBLE_DETECT_PEND_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_PREAMBLE_DETECT_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_PREAMBLE_DETECT_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_PREAMBLE_DETECT_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_BIT 0x08 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_INDEX 2 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_JUMP_BIT 0x10 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_JUMP_INDEX 2 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_JUMP_LSB 4 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_JUMP_MASK 0x10 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_JUMP_MSB 4 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_JUMP_PEND_BIT 0x10 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_JUMP_PEND_INDEX 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_JUMP_PEND_LSB 4 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_JUMP_PEND_MASK 0x10 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_JUMP_PEND_MSB 4 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_JUMP_PEND_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_JUMP_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_JUMP_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_JUMP_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LATCH_BIT 0x80 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LATCH_INDEX 2 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LATCH_LSB 7 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LATCH_MASK 0x80 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LATCH_MSB 7 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LATCH_PEND_BIT 0x80 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LATCH_PEND_INDEX 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LATCH_PEND_LSB 7 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LATCH_PEND_MASK 0x80 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LATCH_PEND_MSB 7 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LATCH_PEND_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LATCH_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LATCH_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LATCH_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_LSB 3 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_MASK 0x08 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_MSB 3 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_PEND_BIT 0x08 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_PEND_INDEX 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_PEND_LSB 3 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_PEND_MASK 0x08 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_PEND_MSB 3 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_PEND_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_RSSI_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_SYNC_DETECT_BIT 0x01 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_SYNC_DETECT_INDEX 2 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_SYNC_DETECT_LSB 0 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_SYNC_DETECT_MASK 0x01 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_SYNC_DETECT_MSB 0 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_SYNC_DETECT_PEND_BIT 0x01 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_SYNC_DETECT_PEND_INDEX 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_SYNC_DETECT_PEND_LSB 0 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_SYNC_DETECT_PEND_MASK 0x01 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_SYNC_DETECT_PEND_MSB 0 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_SYNC_DETECT_PEND_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_SYNC_DETECT_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_SYNC_DETECT_SIZE 1 |
| #define SI446X_CMD_GET_MODEM_STATUS_REP_SYNC_DETECT_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_CRC_ERROR_BIT 0x08 |
| #define SI446X_CMD_GET_PH_STATUS_REP_CRC_ERROR_INDEX 2 |
| #define SI446X_CMD_GET_PH_STATUS_REP_CRC_ERROR_LSB 3 |
| #define SI446X_CMD_GET_PH_STATUS_REP_CRC_ERROR_MASK 0x08 |
| #define SI446X_CMD_GET_PH_STATUS_REP_CRC_ERROR_MSB 3 |
| #define SI446X_CMD_GET_PH_STATUS_REP_CRC_ERROR_PEND_BIT 0x08 |
| #define SI446X_CMD_GET_PH_STATUS_REP_CRC_ERROR_PEND_INDEX 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_CRC_ERROR_PEND_LSB 3 |
| #define SI446X_CMD_GET_PH_STATUS_REP_CRC_ERROR_PEND_MASK 0x08 |
| #define SI446X_CMD_GET_PH_STATUS_REP_CRC_ERROR_PEND_MSB 3 |
| #define SI446X_CMD_GET_PH_STATUS_REP_CRC_ERROR_PEND_SIZE 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_CRC_ERROR_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_CRC_ERROR_SIZE 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_CRC_ERROR_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MATCH_BIT 0x80 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MATCH_INDEX 2 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MATCH_LSB 7 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MATCH_MASK 0x80 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MATCH_MSB 7 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MATCH_PEND_BIT 0x80 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MATCH_PEND_INDEX 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MATCH_PEND_LSB 7 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MATCH_PEND_MASK 0x80 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MATCH_PEND_MSB 7 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MATCH_PEND_SIZE 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MATCH_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MATCH_SIZE 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MATCH_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MISS_BIT 0x40 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MISS_INDEX 2 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MISS_LSB 6 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MISS_MASK 0x40 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MISS_MSB 6 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MISS_PEND_BIT 0x40 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MISS_PEND_INDEX 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MISS_PEND_LSB 6 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MISS_PEND_MASK 0x40 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MISS_PEND_MSB 6 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MISS_PEND_SIZE 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MISS_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MISS_SIZE 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_FILTER_MISS_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_RX_BIT 0x10 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_RX_INDEX 2 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_RX_LSB 4 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_RX_MASK 0x10 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_RX_MSB 4 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_RX_PEND_BIT 0x10 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_RX_PEND_INDEX 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_RX_PEND_LSB 4 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_RX_PEND_MASK 0x10 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_RX_PEND_MSB 4 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_RX_PEND_SIZE 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_RX_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_RX_SIZE 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_RX_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_SENT_BIT 0x20 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_SENT_INDEX 2 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_SENT_LSB 5 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_SENT_MASK 0x20 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_SENT_MSB 5 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_SENT_PEND_BIT 0x20 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_SENT_PEND_INDEX 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_SENT_PEND_LSB 5 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_SENT_PEND_MASK 0x20 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_SENT_PEND_MSB 5 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_SENT_PEND_SIZE 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_SENT_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_SENT_SIZE 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PACKET_SENT_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_PH_PEND_INDEX 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PH_PEND_LSB 0 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PH_PEND_MASK 0xFF |
| #define SI446X_CMD_GET_PH_STATUS_REP_PH_PEND_MSB 7 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PH_PEND_SIZE 8 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PH_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_PH_STATUS_INDEX 2 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PH_STATUS_LSB 0 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PH_STATUS_MASK 0xFF |
| #define SI446X_CMD_GET_PH_STATUS_REP_PH_STATUS_MSB 7 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PH_STATUS_SIZE 8 |
| #define SI446X_CMD_GET_PH_STATUS_REP_PH_STATUS_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_RX_FIFO_ALMOST_FULL_BIT 0x01 |
| #define SI446X_CMD_GET_PH_STATUS_REP_RX_FIFO_ALMOST_FULL_INDEX 2 |
| #define SI446X_CMD_GET_PH_STATUS_REP_RX_FIFO_ALMOST_FULL_LSB 0 |
| #define SI446X_CMD_GET_PH_STATUS_REP_RX_FIFO_ALMOST_FULL_MASK 0x01 |
| #define SI446X_CMD_GET_PH_STATUS_REP_RX_FIFO_ALMOST_FULL_MSB 0 |
| #define SI446X_CMD_GET_PH_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_BIT 0x01 |
| #define SI446X_CMD_GET_PH_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_INDEX 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_LSB 0 |
| #define SI446X_CMD_GET_PH_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_MASK 0x01 |
| #define SI446X_CMD_GET_PH_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_MSB 0 |
| #define SI446X_CMD_GET_PH_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_SIZE 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_RX_FIFO_ALMOST_FULL_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_RX_FIFO_ALMOST_FULL_SIZE 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_RX_FIFO_ALMOST_FULL_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_TX_FIFO_ALMOST_EMPTY_BIT 0x02 |
| #define SI446X_CMD_GET_PH_STATUS_REP_TX_FIFO_ALMOST_EMPTY_INDEX 2 |
| #define SI446X_CMD_GET_PH_STATUS_REP_TX_FIFO_ALMOST_EMPTY_LSB 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_TX_FIFO_ALMOST_EMPTY_MASK 0x02 |
| #define SI446X_CMD_GET_PH_STATUS_REP_TX_FIFO_ALMOST_EMPTY_MSB 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_BIT 0x02 |
| #define SI446X_CMD_GET_PH_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_INDEX 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_LSB 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_MASK 0x02 |
| #define SI446X_CMD_GET_PH_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_MSB 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_SIZE 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_TX_FIFO_ALMOST_EMPTY_PEND_TYPE bitfield |
| #define SI446X_CMD_GET_PH_STATUS_REP_TX_FIFO_ALMOST_EMPTY_SIZE 1 |
| #define SI446X_CMD_GET_PH_STATUS_REP_TX_FIFO_ALMOST_EMPTY_TYPE bitfield |
| #define SI446X_CMD_GET_PROPERTY_ARG_GROUP_INDEX 1 |
| #define SI446X_CMD_GET_PROPERTY_ARG_GROUP_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_ARG_GROUP_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_ARG_GROUP_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_ARG_GROUP_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_ARG_GROUP_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_ARG_GROUP_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_GET_PROPERTY_ARG_NUM_PROPS_INDEX 2 |
| #define SI446X_CMD_GET_PROPERTY_ARG_NUM_PROPS_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_ARG_NUM_PROPS_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_ARG_NUM_PROPS_MAX 16 |
| #define SI446X_CMD_GET_PROPERTY_ARG_NUM_PROPS_MIN 1 |
| #define SI446X_CMD_GET_PROPERTY_ARG_NUM_PROPS_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_ARG_NUM_PROPS_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_ARG_NUM_PROPS_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_ARG_NUM_PROPS_value (((cmd.arg.RAW[2]))) |
| #define SI446X_CMD_GET_PROPERTY_ARG_START_PROP_INDEX 3 |
| #define SI446X_CMD_GET_PROPERTY_ARG_START_PROP_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_ARG_START_PROP_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_ARG_START_PROP_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_ARG_START_PROP_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_ARG_START_PROP_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_ARG_START_PROP_value (((cmd.arg.RAW[3]))) |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA0_INDEX 1 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA0_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA0_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA0_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA0_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA0_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA10_INDEX 11 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA10_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA10_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA10_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA10_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA10_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA11_INDEX 12 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA11_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA11_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA11_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA11_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA11_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA12_INDEX 13 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA12_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA12_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA12_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA12_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA12_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA13_INDEX 14 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA13_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA13_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA13_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA13_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA13_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA14_INDEX 15 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA14_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA14_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA14_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA14_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA14_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA15_INDEX 16 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA15_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA15_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA15_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA15_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA15_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA1_INDEX 2 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA1_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA1_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA1_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA1_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA1_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA2_INDEX 3 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA2_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA2_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA2_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA2_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA2_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA3_INDEX 4 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA3_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA3_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA3_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA3_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA3_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA4_INDEX 5 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA4_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA4_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA4_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA4_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA4_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA5_INDEX 6 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA5_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA5_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA5_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA5_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA5_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA6_INDEX 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA6_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA6_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA6_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA6_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA6_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA7_INDEX 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA7_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA7_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA7_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA7_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA7_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA8_INDEX 9 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA8_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA8_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA8_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA8_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA8_TYPE u8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA9_INDEX 10 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA9_LSB 0 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA9_MASK 0xFF |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA9_MSB 7 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA9_SIZE 8 |
| #define SI446X_CMD_GET_PROPERTY_REP_DATA9_TYPE u8 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_ENUM_HIGH 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_ENUM_LOW 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_ENUM_MED_HIGH 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_ENUM_MED_LOW 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_INDEX 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_LSB 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_MASK 0x60 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_MSB 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_SIZE 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_DRV_STRENGTH_value (((cmd.arg.RAW[7]&0x60))>>5) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_INDEX 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_MASK 0xFF |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_SIZE 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GEN_CONFIG_value (((cmd.arg.RAW[7]))) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_INDEX 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MASK 0xFF |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_32K_CLK 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_ANTENNA_0_SW 22 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_ANTENNA_1_SW 23 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_BOOT_CLK 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_CAL_WUT 13 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_CCA 27 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_CCA_LATCH 37 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_CMD_OVERLAP 10 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_CTS 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_DIV_CLK 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_DONOTHING 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_DRIVE0 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_DRIVE1 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_HOP_TABLE_WRAP 39 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_HOPPED 38 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_INPUT 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_INV_CTS 9 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_INVALID_PREAMBLE 25 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_LOW_BATT 36 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_POR 12 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_RX_DATA 20 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_RX_DATA_CLK 17 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_RX_FIFO_FULL 34 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_RX_RAW_DATA 21 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_RX_STATE 33 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_SDO 11 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_SYNC_WORD_DETECT 26 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_TRISTATE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_TX_DATA_CLK 16 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_TX_FIFO_EMPTY 35 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_TX_STATE 32 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_VALID_PREAMBLE 24 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_ENUM_WUT 14 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_INDEX 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_MASK 0x3F |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_MSB 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_SIZE 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MODE_value (((cmd.arg.RAW[1]&0x3F))) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_BIT 0x40 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_ENUM_PULL_DIS 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_ENUM_PULL_EN 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_INDEX 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_is_true (cmd.arg.RAW[1]&0x40) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_LSB 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_MASK 0x40 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_MSB 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_SIZE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_PULL_CTL_value (((cmd.arg.RAW[1]&0x40))>>6) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_SIZE 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO0_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_INDEX 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MASK 0xFF |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_32K_CLK 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_ANTENNA_0_SW 22 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_ANTENNA_1_SW 23 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_BOOT_CLK 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_CAL_WUT 13 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_CCA 27 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_CCA_LATCH 37 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_CMD_OVERLAP 10 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_CTS 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_DIV_CLK 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_DONOTHING 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_DRIVE0 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_DRIVE1 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_HOP_TABLE_WRAP 39 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_HOPPED 38 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_INPUT 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_INV_CTS 9 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_INVALID_PREAMBLE 25 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_LOW_BATT 36 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_POR 12 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_RX_DATA 20 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_RX_DATA_CLK 17 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_RX_FIFO_FULL 34 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_RX_RAW_DATA 21 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_RX_STATE 33 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_SDO 11 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_SYNC_WORD_DETECT 26 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_TRISTATE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_TX_DATA_CLK 16 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_TX_FIFO_EMPTY 35 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_TX_STATE 32 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_VALID_PREAMBLE 24 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_ENUM_WUT 14 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_INDEX 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_MASK 0x3F |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_MSB 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_SIZE 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MODE_value (((cmd.arg.RAW[2]&0x3F))) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_BIT 0x40 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_ENUM_PULL_DIS 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_ENUM_PULL_EN 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_INDEX 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_is_true (cmd.arg.RAW[2]&0x40) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_LSB 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_MASK 0x40 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_MSB 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_SIZE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_PULL_CTL_value (((cmd.arg.RAW[2]&0x40))>>6) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_SIZE 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO1_value (((cmd.arg.RAW[2]))) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_INDEX 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MASK 0xFF |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_32K_CLK 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_ANTENNA_0_SW 22 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_ANTENNA_1_SW 23 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_BOOT_CLK 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_CAL_WUT 13 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_CCA 27 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_CCA_LATCH 37 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_CMD_OVERLAP 10 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_CTS 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_DIV_CLK 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_DONOTHING 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_DRIVE0 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_DRIVE1 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_HOP_TABLE_WRAP 39 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_HOPPED 38 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_INPUT 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_INV_CTS 9 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_INVALID_PREAMBLE 25 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_LOW_BATT 36 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_POR 12 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_RX_DATA 20 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_RX_DATA_CLK 17 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_RX_FIFO_FULL 34 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_RX_RAW_DATA 21 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_RX_STATE 33 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_SDO 11 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_SYNC_WORD_DETECT 26 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_TRISTATE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_TX_DATA_CLK 16 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_TX_FIFO_EMPTY 35 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_TX_STATE 32 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_VALID_PREAMBLE 24 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_ENUM_WUT 14 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_INDEX 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_MASK 0x3F |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_MSB 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_SIZE 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MODE_value (((cmd.arg.RAW[3]&0x3F))) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_BIT 0x40 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_ENUM_PULL_DIS 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_ENUM_PULL_EN 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_INDEX 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_is_true (cmd.arg.RAW[3]&0x40) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_LSB 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_MASK 0x40 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_MSB 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_SIZE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_PULL_CTL_value (((cmd.arg.RAW[3]&0x40))>>6) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_SIZE 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO2_value (((cmd.arg.RAW[3]))) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_INDEX 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MASK 0xFF |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_32K_CLK 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_ANTENNA_0_SW 22 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_ANTENNA_1_SW 23 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_BOOT_CLK 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_CAL_WUT 13 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_CCA 27 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_CCA_LATCH 37 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_CMD_OVERLAP 10 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_CTS 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_DIV_CLK 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_DONOTHING 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_DRIVE0 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_DRIVE1 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_HOP_TABLE_WRAP 39 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_HOPPED 38 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_INPUT 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_INV_CTS 9 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_INVALID_PREAMBLE 25 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_LOW_BATT 36 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_POR 12 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_RX_DATA 20 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_RX_DATA_CLK 17 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_RX_FIFO_FULL 34 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_RX_RAW_DATA 21 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_RX_STATE 33 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_SDO 11 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_SYNC_WORD_DETECT 26 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_TRISTATE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_TX_DATA_CLK 16 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_TX_FIFO_EMPTY 35 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_TX_STATE 32 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_VALID_PREAMBLE 24 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_ENUM_WUT 14 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_INDEX 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_MASK 0x3F |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_MSB 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_SIZE 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MODE_value (((cmd.arg.RAW[4]&0x3F))) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_BIT 0x40 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_ENUM_PULL_DIS 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_ENUM_PULL_EN 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_INDEX 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_is_true (cmd.arg.RAW[4]&0x40) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_LSB 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_MASK 0x40 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_MSB 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_SIZE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_PULL_CTL_value (((cmd.arg.RAW[4]&0x40))>>6) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_SIZE 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_GPIO3_value (((cmd.arg.RAW[4]))) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_BIT 0x40 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_ENUM_PULL_DIS 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_ENUM_PULL_EN 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_INDEX 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_is_true (cmd.arg.RAW[5]&0x40) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_LSB 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_MASK 0x40 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_MSB 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_SIZE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_DRV_PULL_value (((cmd.arg.RAW[5]&0x40))>>6) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_INDEX 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MASK 0xFF |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_ANTENNA_0_SW 22 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_ANTENNA_1_SW 23 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_CCA 27 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_CTS 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_DIV_CLK 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_DONOTHING 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_DRIVE0 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_DRIVE1 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_INPUT 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_INVALID_PREAMBLE 25 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_NIRQ 39 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_POR 12 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_RX_DATA 20 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_RX_DATA_CLK 17 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_RX_RAW_DATA 21 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_SDO 11 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_SYNC_WORD_DETECT 26 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_TRISTATE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_TX_DATA_CLK 16 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_ENUM_VALID_PREAMBLE 24 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_INDEX 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_MASK 0x3F |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_MSB 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_SIZE 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MODE_value (((cmd.arg.RAW[5]&0x3F))) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_SIZE 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_NIRQ_value (((cmd.arg.RAW[5]))) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_INDEX 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MASK 0xFF |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_32K_CLK 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_ANTENNA_0_SW 22 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_ANTENNA_1_SW 23 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_CCA 27 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_CTS 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_DIV_CLK 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_DONOTHING 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_DRIVE0 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_DRIVE1 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_INPUT 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_INVALID_PREAMBLE 25 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_POR 12 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_RX_DATA 20 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_RX_DATA_CLK 17 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_RX_RAW_DATA 21 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_SDO 11 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_SYNC_WORD_DETECT 26 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_TRISTATE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_TX_DATA_CLK 16 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_VALID_PREAMBLE 24 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_ENUM_WUT 14 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_INDEX 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_MASK 0x3F |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_MSB 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_SIZE 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MODE_value (((cmd.arg.RAW[6]&0x3F))) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_BIT 0x40 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_ENUM_PULL_DIS 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_ENUM_PULL_EN 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_INDEX 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_is_true (cmd.arg.RAW[6]&0x40) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_LSB 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_MASK 0x40 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_MSB 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_SIZE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_PULL_CTL_value (((cmd.arg.RAW[6]&0x40))>>6) |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_SIZE 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_ARG_SDO_value (((cmd.arg.RAW[6]))) |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_ENUM_HIGH 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_ENUM_LOW 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_ENUM_MED_HIGH 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_ENUM_MED_LOW 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_INDEX 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_LSB 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_MASK 0x60 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_MSB 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_SIZE 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_DRV_STRENGTH_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GEN_CONFIG_INDEX 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GEN_CONFIG_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GEN_CONFIG_MASK 0xFF |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GEN_CONFIG_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GEN_CONFIG_SIZE 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GEN_CONFIG_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0_INDEX 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0_MASK 0xFF |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0_SIZE 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0_STATE_BIT 0x80 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0_STATE_INDEX 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0_STATE_LSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0_STATE_MASK 0x80 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0_STATE_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0_STATE_SIZE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0_STATE_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_32K_CLK 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_ANTENNA_0_SW 22 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_ANTENNA_1_SW 23 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_BOOT_CLK 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_CAL_WUT 13 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_CCA 27 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_CCA_LATCH 37 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_CMD_OVERLAP 10 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_CTS 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_DIV_CLK 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_DONOTHING 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_DRIVE0 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_DRIVE1 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_HOP_TABLE_WRAP 39 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_HOPPED 38 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_INPUT 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_INV_CTS 9 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_INVALID_PREAMBLE 25 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_LOW_BATT 36 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_POR 12 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_RX_DATA 20 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_RX_DATA_CLK 17 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_RX_FIFO_FULL 34 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_RX_RAW_DATA 21 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_RX_STATE 33 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_SDO 11 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_SYNC_WORD_DETECT 26 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_TRISTATE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_TX_DATA_CLK 16 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_TX_FIFO_EMPTY 35 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_TX_STATE 32 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_VALID_PREAMBLE 24 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_ENUM_WUT 14 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_INDEX 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_MASK 0x3F |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_MSB 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_SIZE 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO0R_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1_INDEX 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1_MASK 0xFF |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1_SIZE 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1_STATE_BIT 0x80 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1_STATE_INDEX 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1_STATE_LSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1_STATE_MASK 0x80 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1_STATE_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1_STATE_SIZE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1_STATE_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_32K_CLK 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_ANTENNA_0_SW 22 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_ANTENNA_1_SW 23 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_BOOT_CLK 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_CAL_WUT 13 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_CCA 27 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_CCA_LATCH 37 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_CMD_OVERLAP 10 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_CTS 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_DIV_CLK 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_DONOTHING 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_DRIVE0 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_DRIVE1 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_HOP_TABLE_WRAP 39 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_HOPPED 38 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_INPUT 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_INV_CTS 9 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_INVALID_PREAMBLE 25 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_LOW_BATT 36 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_POR 12 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_RX_DATA 20 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_RX_DATA_CLK 17 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_RX_FIFO_FULL 34 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_RX_RAW_DATA 21 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_RX_STATE 33 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_SDO 11 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_SYNC_WORD_DETECT 26 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_TRISTATE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_TX_DATA_CLK 16 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_TX_FIFO_EMPTY 35 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_TX_STATE 32 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_VALID_PREAMBLE 24 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_ENUM_WUT 14 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_INDEX 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_MASK 0x3F |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_MSB 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_SIZE 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO1R_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2_INDEX 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2_MASK 0xFF |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2_SIZE 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2_STATE_BIT 0x80 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2_STATE_INDEX 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2_STATE_LSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2_STATE_MASK 0x80 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2_STATE_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2_STATE_SIZE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2_STATE_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_32K_CLK 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_ANTENNA_0_SW 22 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_ANTENNA_1_SW 23 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_BOOT_CLK 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_CAL_WUT 13 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_CCA 27 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_CCA_LATCH 37 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_CMD_OVERLAP 10 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_CTS 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_DIV_CLK 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_DONOTHING 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_DRIVE0 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_DRIVE1 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_HOP_TABLE_WRAP 39 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_HOPPED 38 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_INPUT 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_INV_CTS 9 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_INVALID_PREAMBLE 25 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_LOW_BATT 36 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_POR 12 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_RX_DATA 20 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_RX_DATA_CLK 17 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_RX_FIFO_FULL 34 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_RX_RAW_DATA 21 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_RX_STATE 33 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_SDO 11 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_SYNC_WORD_DETECT 26 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_TRISTATE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_TX_DATA_CLK 16 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_TX_FIFO_EMPTY 35 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_TX_STATE 32 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_VALID_PREAMBLE 24 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_ENUM_WUT 14 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_INDEX 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_MASK 0x3F |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_MSB 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_SIZE 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO2R_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3_INDEX 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3_MASK 0xFF |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3_SIZE 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_32K_CLK 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_ANTENNA_0_SW 22 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_ANTENNA_1_SW 23 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_BOOT_CLK 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_CAL_WUT 13 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_CCA 27 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_CCA_LATCH 37 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_CMD_OVERLAP 10 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_CTS 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_DIV_CLK 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_DONOTHING 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_DRIVE0 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_DRIVE1 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_HOP_TABLE_WRAP 39 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_HOPPED 38 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_INPUT 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_INV_CTS 9 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_INVALID_PREAMBLE 25 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_LOW_BATT 36 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_POR 12 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_RX_DATA 20 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_RX_DATA_CLK 17 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_RX_FIFO_FULL 34 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_RX_RAW_DATA 21 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_RX_STATE 33 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_SDO 11 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_SYNC_WORD_DETECT 26 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_TRISTATE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_TX_DATA_CLK 16 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_TX_FIFO_EMPTY 35 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_TX_STATE 32 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_VALID_PREAMBLE 24 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_ENUM_WUT 14 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_INDEX 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_MASK 0x3F |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_MSB 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_SIZE 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3R_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3STATE_BIT 0x80 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3STATE_INDEX 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3STATE_LSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3STATE_MASK 0x80 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3STATE_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3STATE_SIZE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_GPIO3STATE_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQ_INDEX 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQ_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQ_MASK 0xFF |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQ_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQ_SIZE 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQ_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_ANTENNA_0_SW 22 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_ANTENNA_1_SW 23 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_CCA 27 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_CTS 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_DIV_CLK 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_DONOTHING 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_DRIVE0 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_DRIVE1 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_INPUT 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_INVALID_PREAMBLE 25 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_NIRQ 39 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_POR 12 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_RX_DATA 20 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_RX_DATA_CLK 17 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_RX_RAW_DATA 21 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_SDO 11 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_SYNC_WORD_DETECT 26 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_TRISTATE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_TX_DATA_CLK 16 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_ENUM_VALID_PREAMBLE 24 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_INDEX 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_MASK 0x3F |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_MSB 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_SIZE 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQR_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQSTATE_BIT 0x80 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQSTATE_INDEX 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQSTATE_LSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQSTATE_MASK 0x80 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQSTATE_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQSTATE_SIZE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_NIRQSTATE_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDO_INDEX 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDO_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDO_MASK 0xFF |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDO_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDO_SIZE 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDO_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_32K_CLK 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_ANTENNA_0_SW 22 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_ANTENNA_1_SW 23 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_CCA 27 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_CTS 8 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_DIV_CLK 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_DONOTHING 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_DRIVE0 2 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_DRIVE1 3 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_INPUT 4 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_INVALID_PREAMBLE 25 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_POR 12 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_RX_DATA 20 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_RX_DATA_CLK 17 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_RX_RAW_DATA 21 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_SDO 11 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_SYNC_WORD_DETECT 26 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_TRISTATE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_TX_DATA_CLK 16 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_VALID_PREAMBLE 24 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_ENUM_WUT 14 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_INDEX 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_LSB 0 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_MASK 0x3F |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_MSB 5 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_SIZE 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOR_TYPE bitfield |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOSTATE_BIT 0x80 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOSTATE_INDEX 6 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOSTATE_LSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOSTATE_MASK 0x80 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOSTATE_MSB 7 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOSTATE_SIZE 1 |
| #define SI446X_CMD_GPIO_PIN_CFG_REP_SDOSTATE_TYPE bitfield |
| #define SI446X_CMD_ID_AGC_OVERRIDE 0xD0 |
| #define SI446X_CMD_ID_CHANGE_STATE 0x34 |
| #define SI446X_CMD_ID_FIFO_INFO 0x15 |
| #define SI446X_CMD_ID_FRR_A_READ 0x50 |
| #define SI446X_CMD_ID_FRR_B_READ 0x51 |
| #define SI446X_CMD_ID_FRR_C_READ 0x53 |
| #define SI446X_CMD_ID_FRR_D_READ 0x57 |
| #define SI446X_CMD_ID_FUNC_INFO 0x10 |
| #define SI446X_CMD_ID_GET_ADC_READING 0x14 |
| #define SI446X_CMD_ID_GET_CHIP_STATUS 0x23 |
| #define SI446X_CMD_ID_GET_INT_STATUS 0x20 |
| #define SI446X_CMD_ID_GET_MODEM_STATUS 0x22 |
| #define SI446X_CMD_ID_GET_PH_STATUS 0x21 |
| #define SI446X_CMD_ID_GET_PROPERTY 0x12 |
| #define SI446X_CMD_ID_GPIO_PIN_CFG 0x13 |
| #define SI446X_CMD_ID_IRCAL 0x17 |
| #define SI446X_CMD_ID_NOP 0x00 |
| #define SI446X_CMD_ID_PACKET_INFO 0x16 |
| #define SI446X_CMD_ID_PART_INFO 0x01 |
| #define SI446X_CMD_ID_POWER_UP 0x02 |
| #define SI446X_CMD_ID_PROTOCOL_CFG 0x18 |
| #define SI446X_CMD_ID_READ_CMD_BUFF 0x44 |
| #define SI446X_CMD_ID_READ_RX_FIFO 0x77 |
| #define SI446X_CMD_ID_REQUEST_DEVICE_STATE 0x33 |
| #define SI446X_CMD_ID_RX_HOP 0x36 |
| #define SI446X_CMD_ID_SET_PROPERTY 0x11 |
| #define SI446X_CMD_ID_START_MFSK 0x35 |
| #define SI446X_CMD_ID_START_RX 0x32 |
| #define SI446X_CMD_ID_START_TX 0x31 |
| #define SI446X_CMD_ID_WRITE_TX_FIFO 0x66 |
| #define SI446X_CMD_IRCAL_ARG_ADC_HIGH_GAIN_BIT 0x01 |
| #define SI446X_CMD_IRCAL_ARG_ADC_HIGH_GAIN_INDEX 4 |
| #define SI446X_CMD_IRCAL_ARG_ADC_HIGH_GAIN_is_true (cmd.arg.RAW[4]&0x1) |
| #define SI446X_CMD_IRCAL_ARG_ADC_HIGH_GAIN_LSB 0 |
| #define SI446X_CMD_IRCAL_ARG_ADC_HIGH_GAIN_MASK 0x01 |
| #define SI446X_CMD_IRCAL_ARG_ADC_HIGH_GAIN_MSB 0 |
| #define SI446X_CMD_IRCAL_ARG_ADC_HIGH_GAIN_SIZE 1 |
| #define SI446X_CMD_IRCAL_ARG_ADC_HIGH_GAIN_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_ADC_HIGH_GAIN_value (((cmd.arg.RAW[4]&0x1))) |
| #define SI446X_CMD_IRCAL_ARG_CLOSE_SHUNT_SWITCH_BIT 0x08 |
| #define SI446X_CMD_IRCAL_ARG_CLOSE_SHUNT_SWITCH_INDEX 3 |
| #define SI446X_CMD_IRCAL_ARG_CLOSE_SHUNT_SWITCH_is_true (cmd.arg.RAW[3]&0x8) |
| #define SI446X_CMD_IRCAL_ARG_CLOSE_SHUNT_SWITCH_LSB 3 |
| #define SI446X_CMD_IRCAL_ARG_CLOSE_SHUNT_SWITCH_MASK 0x08 |
| #define SI446X_CMD_IRCAL_ARG_CLOSE_SHUNT_SWITCH_MSB 3 |
| #define SI446X_CMD_IRCAL_ARG_CLOSE_SHUNT_SWITCH_SIZE 1 |
| #define SI446X_CMD_IRCAL_ARG_CLOSE_SHUNT_SWITCH_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_CLOSE_SHUNT_SWITCH_value (((cmd.arg.RAW[3]&0x8))>>3) |
| #define SI446X_CMD_IRCAL_ARG_COARSE_STEP_SIZE_INDEX 1 |
| #define SI446X_CMD_IRCAL_ARG_COARSE_STEP_SIZE_LSB 0 |
| #define SI446X_CMD_IRCAL_ARG_COARSE_STEP_SIZE_MASK 0x0F |
| #define SI446X_CMD_IRCAL_ARG_COARSE_STEP_SIZE_MAX 15 |
| #define SI446X_CMD_IRCAL_ARG_COARSE_STEP_SIZE_MIN 0 |
| #define SI446X_CMD_IRCAL_ARG_COARSE_STEP_SIZE_MSB 3 |
| #define SI446X_CMD_IRCAL_ARG_COARSE_STEP_SIZE_SIZE 4 |
| #define SI446X_CMD_IRCAL_ARG_COARSE_STEP_SIZE_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_COARSE_STEP_SIZE_value (((cmd.arg.RAW[1]&0xF))) |
| #define SI446X_CMD_IRCAL_ARG_EN_HRMNIC_GEN_BIT 0x80 |
| #define SI446X_CMD_IRCAL_ARG_EN_HRMNIC_GEN_INDEX 3 |
| #define SI446X_CMD_IRCAL_ARG_EN_HRMNIC_GEN_is_true (cmd.arg.RAW[3]&0x80) |
| #define SI446X_CMD_IRCAL_ARG_EN_HRMNIC_GEN_LSB 7 |
| #define SI446X_CMD_IRCAL_ARG_EN_HRMNIC_GEN_MASK 0x80 |
| #define SI446X_CMD_IRCAL_ARG_EN_HRMNIC_GEN_MSB 7 |
| #define SI446X_CMD_IRCAL_ARG_EN_HRMNIC_GEN_SIZE 1 |
| #define SI446X_CMD_IRCAL_ARG_EN_HRMNIC_GEN_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_EN_HRMNIC_GEN_value (((cmd.arg.RAW[3]&0x80))>>7) |
| #define SI446X_CMD_IRCAL_ARG_FINE_STEP_SIZE_INDEX 1 |
| #define SI446X_CMD_IRCAL_ARG_FINE_STEP_SIZE_LSB 4 |
| #define SI446X_CMD_IRCAL_ARG_FINE_STEP_SIZE_MASK 0x30 |
| #define SI446X_CMD_IRCAL_ARG_FINE_STEP_SIZE_MAX 3 |
| #define SI446X_CMD_IRCAL_ARG_FINE_STEP_SIZE_MIN 0 |
| #define SI446X_CMD_IRCAL_ARG_FINE_STEP_SIZE_MSB 5 |
| #define SI446X_CMD_IRCAL_ARG_FINE_STEP_SIZE_SIZE 2 |
| #define SI446X_CMD_IRCAL_ARG_FINE_STEP_SIZE_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_FINE_STEP_SIZE_value (((cmd.arg.RAW[1]&0x30))>>4) |
| #define SI446X_CMD_IRCAL_ARG_INITIAL_PH_AMP_BIT 0x40 |
| #define SI446X_CMD_IRCAL_ARG_INITIAL_PH_AMP_INDEX 1 |
| #define SI446X_CMD_IRCAL_ARG_INITIAL_PH_AMP_is_true (cmd.arg.RAW[1]&0x40) |
| #define SI446X_CMD_IRCAL_ARG_INITIAL_PH_AMP_LSB 6 |
| #define SI446X_CMD_IRCAL_ARG_INITIAL_PH_AMP_MASK 0x40 |
| #define SI446X_CMD_IRCAL_ARG_INITIAL_PH_AMP_MSB 6 |
| #define SI446X_CMD_IRCAL_ARG_INITIAL_PH_AMP_SIZE 1 |
| #define SI446X_CMD_IRCAL_ARG_INITIAL_PH_AMP_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_INITIAL_PH_AMP_value (((cmd.arg.RAW[1]&0x40))>>6) |
| #define SI446X_CMD_IRCAL_ARG_IRCLKDIV_BIT 0x40 |
| #define SI446X_CMD_IRCAL_ARG_IRCLKDIV_INDEX 3 |
| #define SI446X_CMD_IRCAL_ARG_IRCLKDIV_is_true (cmd.arg.RAW[3]&0x40) |
| #define SI446X_CMD_IRCAL_ARG_IRCLKDIV_LSB 6 |
| #define SI446X_CMD_IRCAL_ARG_IRCLKDIV_MASK 0x40 |
| #define SI446X_CMD_IRCAL_ARG_IRCLKDIV_MSB 6 |
| #define SI446X_CMD_IRCAL_ARG_IRCLKDIV_SIZE 1 |
| #define SI446X_CMD_IRCAL_ARG_IRCLKDIV_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_IRCLKDIV_value (((cmd.arg.RAW[3]&0x40))>>6) |
| #define SI446X_CMD_IRCAL_ARG_PGA_GAIN_INDEX 3 |
| #define SI446X_CMD_IRCAL_ARG_PGA_GAIN_LSB 0 |
| #define SI446X_CMD_IRCAL_ARG_PGA_GAIN_MASK 0x07 |
| #define SI446X_CMD_IRCAL_ARG_PGA_GAIN_MSB 2 |
| #define SI446X_CMD_IRCAL_ARG_PGA_GAIN_SIZE 3 |
| #define SI446X_CMD_IRCAL_ARG_PGA_GAIN_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_PGA_GAIN_value (((cmd.arg.RAW[3]&0x7))) |
| #define SI446X_CMD_IRCAL_ARG_RF_SOURCE_PWR_INDEX 3 |
| #define SI446X_CMD_IRCAL_ARG_RF_SOURCE_PWR_LSB 4 |
| #define SI446X_CMD_IRCAL_ARG_RF_SOURCE_PWR_MASK 0x30 |
| #define SI446X_CMD_IRCAL_ARG_RF_SOURCE_PWR_MSB 5 |
| #define SI446X_CMD_IRCAL_ARG_RF_SOURCE_PWR_SIZE 2 |
| #define SI446X_CMD_IRCAL_ARG_RF_SOURCE_PWR_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_RF_SOURCE_PWR_value (((cmd.arg.RAW[3]&0x30))>>4) |
| #define SI446X_CMD_IRCAL_ARG_RSSI_COARSE_AVG_INDEX 2 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_COARSE_AVG_LSB 0 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_COARSE_AVG_MASK 0x03 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_COARSE_AVG_MSB 1 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_COARSE_AVG_SIZE 2 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_COARSE_AVG_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_RSSI_COARSE_AVG_value (((cmd.arg.RAW[2]&0x3))) |
| #define SI446X_CMD_IRCAL_ARG_RSSI_COURSE_AVG_INDEX 2 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_COURSE_AVG_LSB 0 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_COURSE_AVG_MASK 0x03 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_COURSE_AVG_MSB 1 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_COURSE_AVG_SIZE 2 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_COURSE_AVG_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_RSSI_COURSE_AVG_value (((cmd.arg.RAW[2]&0x3))) |
| #define SI446X_CMD_IRCAL_ARG_RSSI_FINE_AVG_INDEX 2 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_FINE_AVG_LSB 4 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_FINE_AVG_MASK 0x30 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_FINE_AVG_MSB 5 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_FINE_AVG_SIZE 2 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_FINE_AVG_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_RSSI_FINE_AVG_value (((cmd.arg.RAW[2]&0x30))>>4) |
| #define SI446X_CMD_IRCAL_ARG_RSSI_READ_DLEAY_INDEX 4 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_READ_DLEAY_LSB 4 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_READ_DLEAY_MASK 0xF0 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_READ_DLEAY_MSB 7 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_READ_DLEAY_SIZE 4 |
| #define SI446X_CMD_IRCAL_ARG_RSSI_READ_DLEAY_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_RSSI_READ_DLEAY_value (((cmd.arg.RAW[4]&0xF0))>>4) |
| #define SI446X_CMD_IRCAL_ARG_RX_CHAIN_SETTING1_INDEX 3 |
| #define SI446X_CMD_IRCAL_ARG_RX_CHAIN_SETTING1_LSB 0 |
| #define SI446X_CMD_IRCAL_ARG_RX_CHAIN_SETTING1_MASK 0xFF |
| #define SI446X_CMD_IRCAL_ARG_RX_CHAIN_SETTING1_MSB 7 |
| #define SI446X_CMD_IRCAL_ARG_RX_CHAIN_SETTING1_SIZE 8 |
| #define SI446X_CMD_IRCAL_ARG_RX_CHAIN_SETTING1_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_RX_CHAIN_SETTING1_value (((cmd.arg.RAW[3]))) |
| #define SI446X_CMD_IRCAL_ARG_RX_CHAIN_SETTING2_INDEX 4 |
| #define SI446X_CMD_IRCAL_ARG_RX_CHAIN_SETTING2_LSB 0 |
| #define SI446X_CMD_IRCAL_ARG_RX_CHAIN_SETTING2_MASK 0xFF |
| #define SI446X_CMD_IRCAL_ARG_RX_CHAIN_SETTING2_MSB 7 |
| #define SI446X_CMD_IRCAL_ARG_RX_CHAIN_SETTING2_SIZE 8 |
| #define SI446X_CMD_IRCAL_ARG_RX_CHAIN_SETTING2_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_RX_CHAIN_SETTING2_value (((cmd.arg.RAW[4]))) |
| #define SI446X_CMD_IRCAL_ARG_SEARCHING_RSSI_AVG_INDEX 2 |
| #define SI446X_CMD_IRCAL_ARG_SEARCHING_RSSI_AVG_LSB 0 |
| #define SI446X_CMD_IRCAL_ARG_SEARCHING_RSSI_AVG_MASK 0xFF |
| #define SI446X_CMD_IRCAL_ARG_SEARCHING_RSSI_AVG_MSB 7 |
| #define SI446X_CMD_IRCAL_ARG_SEARCHING_RSSI_AVG_SIZE 8 |
| #define SI446X_CMD_IRCAL_ARG_SEARCHING_RSSI_AVG_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_SEARCHING_RSSI_AVG_value (((cmd.arg.RAW[2]))) |
| #define SI446X_CMD_IRCAL_ARG_SEARCHING_STEP_SIZE_INDEX 1 |
| #define SI446X_CMD_IRCAL_ARG_SEARCHING_STEP_SIZE_LSB 0 |
| #define SI446X_CMD_IRCAL_ARG_SEARCHING_STEP_SIZE_MASK 0xFF |
| #define SI446X_CMD_IRCAL_ARG_SEARCHING_STEP_SIZE_MSB 7 |
| #define SI446X_CMD_IRCAL_ARG_SEARCHING_STEP_SIZE_SIZE 8 |
| #define SI446X_CMD_IRCAL_ARG_SEARCHING_STEP_SIZE_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_SEARCHING_STEP_SIZE_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_IRCAL_ARG_SKIP_CAL_BIT 0x04 |
| #define SI446X_CMD_IRCAL_ARG_SKIP_CAL_INDEX 2 |
| #define SI446X_CMD_IRCAL_ARG_SKIP_CAL_is_true (cmd.arg.RAW[2]&0x4) |
| #define SI446X_CMD_IRCAL_ARG_SKIP_CAL_LSB 2 |
| #define SI446X_CMD_IRCAL_ARG_SKIP_CAL_MASK 0x04 |
| #define SI446X_CMD_IRCAL_ARG_SKIP_CAL_MSB 2 |
| #define SI446X_CMD_IRCAL_ARG_SKIP_CAL_SIZE 1 |
| #define SI446X_CMD_IRCAL_ARG_SKIP_CAL_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_SKIP_CAL_value (((cmd.arg.RAW[2]&0x4))>>2) |
| #define SI446X_CMD_IRCAL_ARG_SKIP_INIT_SEARCH_STAT_BIT 0x40 |
| #define SI446X_CMD_IRCAL_ARG_SKIP_INIT_SEARCH_STAT_INDEX 2 |
| #define SI446X_CMD_IRCAL_ARG_SKIP_INIT_SEARCH_STAT_is_true (cmd.arg.RAW[2]&0x40) |
| #define SI446X_CMD_IRCAL_ARG_SKIP_INIT_SEARCH_STAT_LSB 6 |
| #define SI446X_CMD_IRCAL_ARG_SKIP_INIT_SEARCH_STAT_MASK 0x40 |
| #define SI446X_CMD_IRCAL_ARG_SKIP_INIT_SEARCH_STAT_MSB 6 |
| #define SI446X_CMD_IRCAL_ARG_SKIP_INIT_SEARCH_STAT_SIZE 1 |
| #define SI446X_CMD_IRCAL_ARG_SKIP_INIT_SEARCH_STAT_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_SKIP_INIT_SEARCH_STAT_value (((cmd.arg.RAW[2]&0x40))>>6) |
| #define SI446X_CMD_IRCAL_ARG_STEP_BY_STEP_BIT 0x80 |
| #define SI446X_CMD_IRCAL_ARG_STEP_BY_STEP_INDEX 2 |
| #define SI446X_CMD_IRCAL_ARG_STEP_BY_STEP_is_true (cmd.arg.RAW[2]&0x80) |
| #define SI446X_CMD_IRCAL_ARG_STEP_BY_STEP_LSB 7 |
| #define SI446X_CMD_IRCAL_ARG_STEP_BY_STEP_MASK 0x80 |
| #define SI446X_CMD_IRCAL_ARG_STEP_BY_STEP_MSB 7 |
| #define SI446X_CMD_IRCAL_ARG_STEP_BY_STEP_SIZE 1 |
| #define SI446X_CMD_IRCAL_ARG_STEP_BY_STEP_TYPE bitfield |
| #define SI446X_CMD_IRCAL_ARG_STEP_BY_STEP_value (((cmd.arg.RAW[2]&0x80))>>7) |
| #define SI446X_CMD_IRCAL_REP_CAL_STATE_INDEX 1 |
| #define SI446X_CMD_IRCAL_REP_CAL_STATE_LSB 0 |
| #define SI446X_CMD_IRCAL_REP_CAL_STATE_MASK 0xFF |
| #define SI446X_CMD_IRCAL_REP_CAL_STATE_MSB 7 |
| #define SI446X_CMD_IRCAL_REP_CAL_STATE_SIZE 8 |
| #define SI446X_CMD_IRCAL_REP_CAL_STATE_TYPE u8 |
| #define SI446X_CMD_IRCAL_REP_DIR_CH_INDEX 3 |
| #define SI446X_CMD_IRCAL_REP_DIR_CH_LSB 0 |
| #define SI446X_CMD_IRCAL_REP_DIR_CH_MASK 0xFF |
| #define SI446X_CMD_IRCAL_REP_DIR_CH_MSB 7 |
| #define SI446X_CMD_IRCAL_REP_DIR_CH_SIZE 8 |
| #define SI446X_CMD_IRCAL_REP_DIR_CH_TYPE u8 |
| #define SI446X_CMD_IRCAL_REP_RSSI_INDEX 2 |
| #define SI446X_CMD_IRCAL_REP_RSSI_LSB 0 |
| #define SI446X_CMD_IRCAL_REP_RSSI_MASK 0xFF |
| #define SI446X_CMD_IRCAL_REP_RSSI_MSB 7 |
| #define SI446X_CMD_IRCAL_REP_RSSI_SIZE 8 |
| #define SI446X_CMD_IRCAL_REP_RSSI_TYPE u8 |
| #define SI446X_CMD_PACKET_INFO_ARG_FIELD_NUM_INDEX 1 |
| #define SI446X_CMD_PACKET_INFO_ARG_FIELD_NUM_LSB 0 |
| #define SI446X_CMD_PACKET_INFO_ARG_FIELD_NUM_MASK 0x1F |
| #define SI446X_CMD_PACKET_INFO_ARG_FIELD_NUM_MSB 4 |
| #define SI446X_CMD_PACKET_INFO_ARG_FIELD_NUM_SIZE 5 |
| #define SI446X_CMD_PACKET_INFO_ARG_FIELD_NUM_TYPE bitfield |
| #define SI446X_CMD_PACKET_INFO_ARG_FIELD_NUM_value (((cmd.arg.RAW[1]&0x1F))) |
| #define SI446X_CMD_PACKET_INFO_ARG_FIELD_NUMBER_INDEX 1 |
| #define SI446X_CMD_PACKET_INFO_ARG_FIELD_NUMBER_LSB 0 |
| #define SI446X_CMD_PACKET_INFO_ARG_FIELD_NUMBER_MASK 0xFF |
| #define SI446X_CMD_PACKET_INFO_ARG_FIELD_NUMBER_MSB 7 |
| #define SI446X_CMD_PACKET_INFO_ARG_FIELD_NUMBER_SIZE 8 |
| #define SI446X_CMD_PACKET_INFO_ARG_FIELD_NUMBER_TYPE bitfield |
| #define SI446X_CMD_PACKET_INFO_ARG_FIELD_NUMBER_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_DIFF_INDEX 4 |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_DIFF_LSB 0 |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_DIFF_MASK 0xFFFF |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_DIFF_MAX 32767 |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_DIFF_MIN -32768 |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_DIFF_MSB 15 |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_DIFF_SIZE 16 |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_DIFF_TYPE i16 |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_DIFF_value (((i16)(cmd.arg.RAW_i16[2]))) |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_INDEX 2 |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_LSB 0 |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_MASK 0xFFFF |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_MAX 8191 |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_MIN 1 |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_MSB 15 |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_SIZE 16 |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_TYPE u16 |
| #define SI446X_CMD_PACKET_INFO_ARG_LEN_value (((cmd.arg.RAW_u16[1]))) |
| #define SI446X_CMD_PACKET_INFO_REP_LENGTH_15_8_INDEX 1 |
| #define SI446X_CMD_PACKET_INFO_REP_LENGTH_15_8_LSB 0 |
| #define SI446X_CMD_PACKET_INFO_REP_LENGTH_15_8_MASK 0xFF |
| #define SI446X_CMD_PACKET_INFO_REP_LENGTH_15_8_MSB 7 |
| #define SI446X_CMD_PACKET_INFO_REP_LENGTH_15_8_SIZE 8 |
| #define SI446X_CMD_PACKET_INFO_REP_LENGTH_15_8_TYPE u8 |
| #define SI446X_CMD_PACKET_INFO_REP_LENGTH_7_0_INDEX 2 |
| #define SI446X_CMD_PACKET_INFO_REP_LENGTH_7_0_LSB 0 |
| #define SI446X_CMD_PACKET_INFO_REP_LENGTH_7_0_MASK 0xFF |
| #define SI446X_CMD_PACKET_INFO_REP_LENGTH_7_0_MSB 7 |
| #define SI446X_CMD_PACKET_INFO_REP_LENGTH_7_0_SIZE 8 |
| #define SI446X_CMD_PACKET_INFO_REP_LENGTH_7_0_TYPE u8 |
| #define SI446X_CMD_PART_INFO_REP_CHIPREV_INDEX 1 |
| #define SI446X_CMD_PART_INFO_REP_CHIPREV_LSB 0 |
| #define SI446X_CMD_PART_INFO_REP_CHIPREV_MASK 0xFF |
| #define SI446X_CMD_PART_INFO_REP_CHIPREV_MSB 7 |
| #define SI446X_CMD_PART_INFO_REP_CHIPREV_SIZE 8 |
| #define SI446X_CMD_PART_INFO_REP_CHIPREV_TYPE u8 |
| #define SI446X_CMD_PART_INFO_REP_CUSTOMER_INDEX 7 |
| #define SI446X_CMD_PART_INFO_REP_CUSTOMER_LSB 0 |
| #define SI446X_CMD_PART_INFO_REP_CUSTOMER_MASK 0xFF |
| #define SI446X_CMD_PART_INFO_REP_CUSTOMER_MSB 7 |
| #define SI446X_CMD_PART_INFO_REP_CUSTOMER_SIZE 8 |
| #define SI446X_CMD_PART_INFO_REP_CUSTOMER_TYPE u8 |
| #define SI446X_CMD_PART_INFO_REP_ID_INDEX 5 |
| #define SI446X_CMD_PART_INFO_REP_ID_LSB 0 |
| #define SI446X_CMD_PART_INFO_REP_ID_MASK 0xFFFF |
| #define SI446X_CMD_PART_INFO_REP_ID_MSB 15 |
| #define SI446X_CMD_PART_INFO_REP_ID_SIZE 16 |
| #define SI446X_CMD_PART_INFO_REP_ID_TYPE u16 |
| #define SI446X_CMD_PART_INFO_REP_PART_INDEX 2 |
| #define SI446X_CMD_PART_INFO_REP_PART_LSB 0 |
| #define SI446X_CMD_PART_INFO_REP_PART_MASK 0xFFFF |
| #define SI446X_CMD_PART_INFO_REP_PART_MSB 15 |
| #define SI446X_CMD_PART_INFO_REP_PART_SIZE 16 |
| #define SI446X_CMD_PART_INFO_REP_PART_TYPE u16 |
| #define SI446X_CMD_PART_INFO_REP_PBUILD_INDEX 4 |
| #define SI446X_CMD_PART_INFO_REP_PBUILD_LSB 0 |
| #define SI446X_CMD_PART_INFO_REP_PBUILD_MASK 0xFF |
| #define SI446X_CMD_PART_INFO_REP_PBUILD_MSB 7 |
| #define SI446X_CMD_PART_INFO_REP_PBUILD_SIZE 8 |
| #define SI446X_CMD_PART_INFO_REP_PBUILD_TYPE u8 |
| #define SI446X_CMD_PART_INFO_REP_ROMID_INDEX 8 |
| #define SI446X_CMD_PART_INFO_REP_ROMID_LSB 0 |
| #define SI446X_CMD_PART_INFO_REP_ROMID_MASK 0xFF |
| #define SI446X_CMD_PART_INFO_REP_ROMID_MSB 7 |
| #define SI446X_CMD_PART_INFO_REP_ROMID_SIZE 8 |
| #define SI446X_CMD_PART_INFO_REP_ROMID_TYPE u8 |
| #define SI446X_CMD_POWER_UP_ARG_BOOT_OPTIONS_INDEX 1 |
| #define SI446X_CMD_POWER_UP_ARG_BOOT_OPTIONS_LSB 0 |
| #define SI446X_CMD_POWER_UP_ARG_BOOT_OPTIONS_MASK 0xFF |
| #define SI446X_CMD_POWER_UP_ARG_BOOT_OPTIONS_MSB 7 |
| #define SI446X_CMD_POWER_UP_ARG_BOOT_OPTIONS_SIZE 8 |
| #define SI446X_CMD_POWER_UP_ARG_BOOT_OPTIONS_TYPE bitfield |
| #define SI446X_CMD_POWER_UP_ARG_BOOT_OPTIONS_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_POWER_UP_ARG_FUNC_ENUM_BOOT 0 |
| #define SI446X_CMD_POWER_UP_ARG_FUNC_ENUM_MAIN 1 |
| #define SI446X_CMD_POWER_UP_ARG_FUNC_INDEX 1 |
| #define SI446X_CMD_POWER_UP_ARG_FUNC_LSB 0 |
| #define SI446X_CMD_POWER_UP_ARG_FUNC_MASK 0x3F |
| #define SI446X_CMD_POWER_UP_ARG_FUNC_MSB 5 |
| #define SI446X_CMD_POWER_UP_ARG_FUNC_SIZE 6 |
| #define SI446X_CMD_POWER_UP_ARG_FUNC_TYPE bitfield |
| #define SI446X_CMD_POWER_UP_ARG_FUNC_value (((cmd.arg.RAW[1]&0x3F))) |
| #define SI446X_CMD_POWER_UP_ARG_PATCH_BIT 0x80 |
| #define SI446X_CMD_POWER_UP_ARG_PATCH_INDEX 1 |
| #define SI446X_CMD_POWER_UP_ARG_PATCH_is_true (cmd.arg.RAW[1]&0x80) |
| #define SI446X_CMD_POWER_UP_ARG_PATCH_LSB 7 |
| #define SI446X_CMD_POWER_UP_ARG_PATCH_MASK 0x80 |
| #define SI446X_CMD_POWER_UP_ARG_PATCH_MSB 7 |
| #define SI446X_CMD_POWER_UP_ARG_PATCH_SIZE 1 |
| #define SI446X_CMD_POWER_UP_ARG_PATCH_TYPE bitfield |
| #define SI446X_CMD_POWER_UP_ARG_PATCH_value (((cmd.arg.RAW[1]&0x80))>>7) |
| #define SI446X_CMD_POWER_UP_ARG_TCXO_BIT 0x01 |
| #define SI446X_CMD_POWER_UP_ARG_TCXO_INDEX 2 |
| #define SI446X_CMD_POWER_UP_ARG_TCXO_is_true (cmd.arg.RAW[2]&0x1) |
| #define SI446X_CMD_POWER_UP_ARG_TCXO_LSB 0 |
| #define SI446X_CMD_POWER_UP_ARG_TCXO_MASK 0x01 |
| #define SI446X_CMD_POWER_UP_ARG_TCXO_MSB 0 |
| #define SI446X_CMD_POWER_UP_ARG_TCXO_SIZE 1 |
| #define SI446X_CMD_POWER_UP_ARG_TCXO_TYPE bitfield |
| #define SI446X_CMD_POWER_UP_ARG_TCXO_value (((cmd.arg.RAW[2]&0x1))) |
| #define SI446X_CMD_POWER_UP_ARG_XO_FREQ_INDEX 3 |
| #define SI446X_CMD_POWER_UP_ARG_XO_FREQ_LSB 0 |
| #define SI446X_CMD_POWER_UP_ARG_XO_FREQ_MASK 0xFFFFFFFF |
| #define SI446X_CMD_POWER_UP_ARG_XO_FREQ_MAX 32000000 |
| #define SI446X_CMD_POWER_UP_ARG_XO_FREQ_MIN 25000000 |
| #define SI446X_CMD_POWER_UP_ARG_XO_FREQ_MSB 31 |
| #define SI446X_CMD_POWER_UP_ARG_XO_FREQ_SIZE 32 |
| #define SI446X_CMD_POWER_UP_ARG_XO_FREQ_TYPE u32 |
| #define SI446X_CMD_POWER_UP_ARG_XO_FREQ_value (((cmd.arg.RAW_u32[0]))) |
| #define SI446X_CMD_POWER_UP_ARG_XTAL_OPTIONS_INDEX 2 |
| #define SI446X_CMD_POWER_UP_ARG_XTAL_OPTIONS_LSB 0 |
| #define SI446X_CMD_POWER_UP_ARG_XTAL_OPTIONS_MASK 0xFF |
| #define SI446X_CMD_POWER_UP_ARG_XTAL_OPTIONS_MSB 7 |
| #define SI446X_CMD_POWER_UP_ARG_XTAL_OPTIONS_SIZE 8 |
| #define SI446X_CMD_POWER_UP_ARG_XTAL_OPTIONS_TYPE bitfield |
| #define SI446X_CMD_POWER_UP_ARG_XTAL_OPTIONS_value (((cmd.arg.RAW[2]))) |
| #define SI446X_CMD_PROTOCOL_CFG_ARG_PROTOCOL_ENUM_GENERIC 0 |
| #define SI446X_CMD_PROTOCOL_CFG_ARG_PROTOCOL_ENUM_IEEE802154G 1 |
| #define SI446X_CMD_PROTOCOL_CFG_ARG_PROTOCOL_INDEX 1 |
| #define SI446X_CMD_PROTOCOL_CFG_ARG_PROTOCOL_LSB 0 |
| #define SI446X_CMD_PROTOCOL_CFG_ARG_PROTOCOL_MASK 0xFF |
| #define SI446X_CMD_PROTOCOL_CFG_ARG_PROTOCOL_MSB 7 |
| #define SI446X_CMD_PROTOCOL_CFG_ARG_PROTOCOL_SIZE 8 |
| #define SI446X_CMD_PROTOCOL_CFG_ARG_PROTOCOL_TYPE u8 |
| #define SI446X_CMD_PROTOCOL_CFG_ARG_PROTOCOL_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF0_INDEX 1 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF0_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF0_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF0_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF0_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF0_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF10_INDEX 11 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF10_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF10_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF10_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF10_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF10_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF11_INDEX 12 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF11_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF11_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF11_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF11_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF11_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF12_INDEX 13 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF12_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF12_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF12_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF12_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF12_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF13_INDEX 14 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF13_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF13_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF13_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF13_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF13_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF14_INDEX 15 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF14_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF14_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF14_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF14_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF14_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF15_INDEX 16 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF15_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF15_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF15_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF15_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF15_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF1_INDEX 2 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF1_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF1_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF1_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF1_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF1_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF2_INDEX 3 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF2_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF2_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF2_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF2_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF2_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF3_INDEX 4 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF3_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF3_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF3_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF3_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF3_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF4_INDEX 5 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF4_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF4_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF4_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF4_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF4_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF5_INDEX 6 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF5_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF5_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF5_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF5_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF5_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF6_INDEX 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF6_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF6_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF6_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF6_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF6_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF7_INDEX 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF7_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF7_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF7_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF7_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF7_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF8_INDEX 9 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF8_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF8_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF8_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF8_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF8_TYPE u8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF9_INDEX 10 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF9_LSB 0 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF9_MASK 0xFF |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF9_MSB 7 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF9_SIZE 8 |
| #define SI446X_CMD_READ_CMD_BUFF_REP_CMD_BUFF9_TYPE u8 |
| #define SI446X_CMD_REPLY_COUNT_AGC_OVERRIDE 0 |
| #define SI446X_CMD_REPLY_COUNT_CHANGE_STATE 0 |
| #define SI446X_CMD_REPLY_COUNT_FIFO_INFO 2 |
| #define SI446X_CMD_REPLY_COUNT_FRR_A_READ 3 |
| #define SI446X_CMD_REPLY_COUNT_FRR_B_READ 3 |
| #define SI446X_CMD_REPLY_COUNT_FRR_C_READ 3 |
| #define SI446X_CMD_REPLY_COUNT_FRR_D_READ 3 |
| #define SI446X_CMD_REPLY_COUNT_FUNC_INFO 6 |
| #define SI446X_CMD_REPLY_COUNT_GET_ADC_READING 8 |
| #define SI446X_CMD_REPLY_COUNT_GET_CHIP_STATUS 3 |
| #define SI446X_CMD_REPLY_COUNT_GET_INT_STATUS 8 |
| #define SI446X_CMD_REPLY_COUNT_GET_MODEM_STATUS 8 |
| #define SI446X_CMD_REPLY_COUNT_GET_PH_STATUS 2 |
| #define SI446X_CMD_REPLY_COUNT_GET_PROPERTY 16 |
| #define SI446X_CMD_REPLY_COUNT_GPIO_PIN_CFG 7 |
| #define SI446X_CMD_REPLY_COUNT_IRCAL 3 |
| #define SI446X_CMD_REPLY_COUNT_NOP 0 |
| #define SI446X_CMD_REPLY_COUNT_PACKET_INFO 2 |
| #define SI446X_CMD_REPLY_COUNT_PART_INFO 8 |
| #define SI446X_CMD_REPLY_COUNT_POWER_UP 0 |
| #define SI446X_CMD_REPLY_COUNT_PROTOCOL_CFG 0 |
| #define SI446X_CMD_REPLY_COUNT_READ_CMD_BUFF 16 |
| #define SI446X_CMD_REPLY_COUNT_READ_RX_FIFO 0 |
| #define SI446X_CMD_REPLY_COUNT_REQUEST_DEVICE_STATE 2 |
| #define SI446X_CMD_REPLY_COUNT_RX_HOP 0 |
| #define SI446X_CMD_REPLY_COUNT_SET_PROPERTY 0 |
| #define SI446X_CMD_REPLY_COUNT_START_MFSK 0 |
| #define SI446X_CMD_REPLY_COUNT_START_RX 0 |
| #define SI446X_CMD_REPLY_COUNT_START_TX 0 |
| #define SI446X_CMD_REPLY_COUNT_WRITE_TX_FIFO 0 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_CURR_STATE_INDEX 1 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_CURR_STATE_LSB 0 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_CURR_STATE_MASK 0xFF |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_CURR_STATE_MSB 7 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_CURR_STATE_SIZE 8 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_CURR_STATE_TYPE bitfield |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_CURRENT_CHANNEL_INDEX 2 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_CURRENT_CHANNEL_LSB 0 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_CURRENT_CHANNEL_MASK 0xFF |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_CURRENT_CHANNEL_MSB 7 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_CURRENT_CHANNEL_SIZE 8 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_CURRENT_CHANNEL_TYPE u8 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_NOCHANGE 0 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_READY 3 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_READY2 4 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_RX 8 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_RX_TUNE 6 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_SLEEP 1 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_SPI_ACTIVE 2 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_TX 7 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_ENUM_TX_TUNE 5 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_INDEX 1 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_LSB 0 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_MASK 0x0F |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_MSB 3 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_SIZE 4 |
| #define SI446X_CMD_REQUEST_DEVICE_STATE_REP_MAIN_STATE_TYPE bitfield |
| #define SI446X_CMD_RX_HOP_ARG_FRAC0_INDEX 4 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC0_LSB 0 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC0_MASK 0xFF |
| #define SI446X_CMD_RX_HOP_ARG_FRAC0_MAX 255 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC0_MIN 0 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC0_MSB 7 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC0_SIZE 8 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC0_TYPE u8 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC0_value (((cmd.arg.RAW[4]))) |
| #define SI446X_CMD_RX_HOP_ARG_FRAC1_INDEX 3 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC1_LSB 0 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC1_MASK 0xFF |
| #define SI446X_CMD_RX_HOP_ARG_FRAC1_MAX 255 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC1_MIN 0 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC1_MSB 7 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC1_SIZE 8 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC1_TYPE u8 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC1_value (((cmd.arg.RAW[3]))) |
| #define SI446X_CMD_RX_HOP_ARG_FRAC2_INDEX 2 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC2_LSB 0 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC2_MASK 0xFF |
| #define SI446X_CMD_RX_HOP_ARG_FRAC2_MAX 15 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC2_MIN 0 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC2_MSB 7 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC2_SIZE 8 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC2_TYPE u8 |
| #define SI446X_CMD_RX_HOP_ARG_FRAC2_value (((cmd.arg.RAW[2]))) |
| #define SI446X_CMD_RX_HOP_ARG_INTE_INDEX 1 |
| #define SI446X_CMD_RX_HOP_ARG_INTE_LSB 0 |
| #define SI446X_CMD_RX_HOP_ARG_INTE_MASK 0xFF |
| #define SI446X_CMD_RX_HOP_ARG_INTE_MAX 127 |
| #define SI446X_CMD_RX_HOP_ARG_INTE_MIN 0 |
| #define SI446X_CMD_RX_HOP_ARG_INTE_MSB 7 |
| #define SI446X_CMD_RX_HOP_ARG_INTE_SIZE 8 |
| #define SI446X_CMD_RX_HOP_ARG_INTE_TYPE u8 |
| #define SI446X_CMD_RX_HOP_ARG_INTE_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT0_INDEX 6 |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT0_LSB 0 |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT0_MASK 0xFF |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT0_MAX 255 |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT0_MIN 0 |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT0_MSB 7 |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT0_SIZE 8 |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT0_TYPE u8 |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT0_value (((cmd.arg.RAW[6]))) |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT1_INDEX 5 |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT1_LSB 0 |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT1_MASK 0xFF |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT1_MAX 255 |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT1_MIN 0 |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT1_MSB 7 |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT1_SIZE 8 |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT1_TYPE u8 |
| #define SI446X_CMD_RX_HOP_ARG_VCO_CNT1_value (((cmd.arg.RAW[5]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA0_INDEX 4 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA0_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA0_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA0_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA0_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA0_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA0_value (((cmd.arg.RAW[4]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA10_INDEX 14 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA10_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA10_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA10_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA10_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA10_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA10_value (((cmd.arg.RAW[14]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA11_INDEX 15 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA11_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA11_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA11_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA11_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA11_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA11_value (((cmd.arg.RAW[15]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA1_INDEX 5 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA1_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA1_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA1_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA1_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA1_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA1_value (((cmd.arg.RAW[5]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA2_INDEX 6 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA2_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA2_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA2_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA2_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA2_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA2_value (((cmd.arg.RAW[6]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA3_INDEX 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA3_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA3_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA3_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA3_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA3_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA3_value (((cmd.arg.RAW[7]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA4_INDEX 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA4_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA4_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA4_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA4_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA4_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA4_value (((cmd.arg.RAW[8]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA5_INDEX 9 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA5_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA5_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA5_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA5_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA5_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA5_value (((cmd.arg.RAW[9]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA6_INDEX 10 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA6_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA6_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA6_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA6_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA6_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA6_value (((cmd.arg.RAW[10]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA7_INDEX 11 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA7_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA7_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA7_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA7_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA7_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA7_value (((cmd.arg.RAW[11]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA8_INDEX 12 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA8_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA8_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA8_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA8_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA8_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA8_value (((cmd.arg.RAW[12]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA9_INDEX 13 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA9_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA9_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA9_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA9_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA9_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_DATA9_value (((cmd.arg.RAW[13]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_GROUP_INDEX 1 |
| #define SI446X_CMD_SET_PROPERTY_ARG_GROUP_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_GROUP_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_GROUP_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_GROUP_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_GROUP_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_GROUP_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_NUM_PROPS_INDEX 2 |
| #define SI446X_CMD_SET_PROPERTY_ARG_NUM_PROPS_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_NUM_PROPS_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_NUM_PROPS_MAX 12 |
| #define SI446X_CMD_SET_PROPERTY_ARG_NUM_PROPS_MIN 1 |
| #define SI446X_CMD_SET_PROPERTY_ARG_NUM_PROPS_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_NUM_PROPS_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_NUM_PROPS_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_NUM_PROPS_value (((cmd.arg.RAW[2]))) |
| #define SI446X_CMD_SET_PROPERTY_ARG_START_PROP_INDEX 3 |
| #define SI446X_CMD_SET_PROPERTY_ARG_START_PROP_LSB 0 |
| #define SI446X_CMD_SET_PROPERTY_ARG_START_PROP_MASK 0xFF |
| #define SI446X_CMD_SET_PROPERTY_ARG_START_PROP_MSB 7 |
| #define SI446X_CMD_SET_PROPERTY_ARG_START_PROP_SIZE 8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_START_PROP_TYPE u8 |
| #define SI446X_CMD_SET_PROPERTY_ARG_START_PROP_value (((cmd.arg.RAW[3]))) |
| #define SI446X_CMD_START_MFSK_ARG_DIR_MODE_CFG_INDEX 1 |
| #define SI446X_CMD_START_MFSK_ARG_DIR_MODE_CFG_LSB 0 |
| #define SI446X_CMD_START_MFSK_ARG_DIR_MODE_CFG_MASK 0xFF |
| #define SI446X_CMD_START_MFSK_ARG_DIR_MODE_CFG_MSB 7 |
| #define SI446X_CMD_START_MFSK_ARG_DIR_MODE_CFG_SIZE 8 |
| #define SI446X_CMD_START_MFSK_ARG_DIR_MODE_CFG_TYPE bitfield |
| #define SI446X_CMD_START_MFSK_ARG_DIR_MODE_CFG_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_START_MFSK_ARG_FREQ_OFFSET_INDEX 2 |
| #define SI446X_CMD_START_MFSK_ARG_FREQ_OFFSET_LSB 0 |
| #define SI446X_CMD_START_MFSK_ARG_FREQ_OFFSET_MASK 0xFFFF |
| #define SI446X_CMD_START_MFSK_ARG_FREQ_OFFSET_MSB 15 |
| #define SI446X_CMD_START_MFSK_ARG_FREQ_OFFSET_SIZE 16 |
| #define SI446X_CMD_START_MFSK_ARG_FREQ_OFFSET_TYPE u16 |
| #define SI446X_CMD_START_MFSK_ARG_FREQ_OFFSET_value (((cmd.arg.RAW_u16[1]))) |
| #define SI446X_CMD_START_MFSK_ARG_INV_DATA_BIT 0x40 |
| #define SI446X_CMD_START_MFSK_ARG_INV_DATA_INDEX 1 |
| #define SI446X_CMD_START_MFSK_ARG_INV_DATA_is_true (cmd.arg.RAW[1]&0x40) |
| #define SI446X_CMD_START_MFSK_ARG_INV_DATA_LSB 6 |
| #define SI446X_CMD_START_MFSK_ARG_INV_DATA_MASK 0x40 |
| #define SI446X_CMD_START_MFSK_ARG_INV_DATA_MSB 6 |
| #define SI446X_CMD_START_MFSK_ARG_INV_DATA_SIZE 1 |
| #define SI446X_CMD_START_MFSK_ARG_INV_DATA_TYPE bitfield |
| #define SI446X_CMD_START_MFSK_ARG_INV_DATA_value (((cmd.arg.RAW[1]&0x40))>>6) |
| #define SI446X_CMD_START_MFSK_ARG_MSB_FIRST_BIT 0x02 |
| #define SI446X_CMD_START_MFSK_ARG_MSB_FIRST_ENUM_LSB_FIRST 0 |
| #define SI446X_CMD_START_MFSK_ARG_MSB_FIRST_ENUM_MSB_FIRST 1 |
| #define SI446X_CMD_START_MFSK_ARG_MSB_FIRST_INDEX 1 |
| #define SI446X_CMD_START_MFSK_ARG_MSB_FIRST_is_true (cmd.arg.RAW[1]&0x2) |
| #define SI446X_CMD_START_MFSK_ARG_MSB_FIRST_LSB 1 |
| #define SI446X_CMD_START_MFSK_ARG_MSB_FIRST_MASK 0x02 |
| #define SI446X_CMD_START_MFSK_ARG_MSB_FIRST_MSB 1 |
| #define SI446X_CMD_START_MFSK_ARG_MSB_FIRST_SIZE 1 |
| #define SI446X_CMD_START_MFSK_ARG_MSB_FIRST_TYPE bitfield |
| #define SI446X_CMD_START_MFSK_ARG_MSB_FIRST_value (((cmd.arg.RAW[1]&0x2))>>1) |
| #define SI446X_CMD_START_MFSK_ARG_SCALE_FACTOR_INDEX 1 |
| #define SI446X_CMD_START_MFSK_ARG_SCALE_FACTOR_LSB 4 |
| #define SI446X_CMD_START_MFSK_ARG_SCALE_FACTOR_MASK 0x30 |
| #define SI446X_CMD_START_MFSK_ARG_SCALE_FACTOR_MSB 5 |
| #define SI446X_CMD_START_MFSK_ARG_SCALE_FACTOR_SIZE 2 |
| #define SI446X_CMD_START_MFSK_ARG_SCALE_FACTOR_TYPE bitfield |
| #define SI446X_CMD_START_MFSK_ARG_SCALE_FACTOR_value (((cmd.arg.RAW[1]&0x30))>>4) |
| #define SI446X_CMD_START_RX_ARG_CHANNEL_INDEX 1 |
| #define SI446X_CMD_START_RX_ARG_CHANNEL_LSB 0 |
| #define SI446X_CMD_START_RX_ARG_CHANNEL_MASK 0xFF |
| #define SI446X_CMD_START_RX_ARG_CHANNEL_MAX 255 |
| #define SI446X_CMD_START_RX_ARG_CHANNEL_MIN 0 |
| #define SI446X_CMD_START_RX_ARG_CHANNEL_MSB 7 |
| #define SI446X_CMD_START_RX_ARG_CHANNEL_SIZE 8 |
| #define SI446X_CMD_START_RX_ARG_CHANNEL_TYPE u8 |
| #define SI446X_CMD_START_RX_ARG_CHANNEL_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_START_RX_ARG_CONDITION_INDEX 2 |
| #define SI446X_CMD_START_RX_ARG_CONDITION_LSB 0 |
| #define SI446X_CMD_START_RX_ARG_CONDITION_MASK 0xFF |
| #define SI446X_CMD_START_RX_ARG_CONDITION_MSB 7 |
| #define SI446X_CMD_START_RX_ARG_CONDITION_SIZE 8 |
| #define SI446X_CMD_START_RX_ARG_CONDITION_TYPE bitfield |
| #define SI446X_CMD_START_RX_ARG_CONDITION_value (((cmd.arg.RAW[2]))) |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE1_INDEX 5 |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE1_LSB 0 |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE1_MASK 0xFF |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE1_MSB 7 |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE1_SIZE 8 |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE1_TYPE bitfield |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE1_value (((cmd.arg.RAW[5]))) |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE2_INDEX 6 |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE2_LSB 0 |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE2_MASK 0xFF |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE2_MSB 7 |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE2_SIZE 8 |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE2_TYPE bitfield |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE2_value (((cmd.arg.RAW[6]))) |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE3_INDEX 7 |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE3_LSB 0 |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE3_MASK 0xFF |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE3_MSB 7 |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE3_SIZE 8 |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE3_TYPE bitfield |
| #define SI446X_CMD_START_RX_ARG_NEXT_STATE3_value (((cmd.arg.RAW[7]))) |
| #define SI446X_CMD_START_RX_ARG_RX_LEN_INDEX 3 |
| #define SI446X_CMD_START_RX_ARG_RX_LEN_LSB 0 |
| #define SI446X_CMD_START_RX_ARG_RX_LEN_MASK 0xFFFF |
| #define SI446X_CMD_START_RX_ARG_RX_LEN_MAX 8191 |
| #define SI446X_CMD_START_RX_ARG_RX_LEN_MIN 0 |
| #define SI446X_CMD_START_RX_ARG_RX_LEN_MSB 15 |
| #define SI446X_CMD_START_RX_ARG_RX_LEN_SIZE 16 |
| #define SI446X_CMD_START_RX_ARG_RX_LEN_TYPE u16 |
| #define SI446X_CMD_START_RX_ARG_RX_LEN_value (((cmd.arg.RAW_u16[1]))) |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_NOCHANGE 0 |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_READY 3 |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_READY2 4 |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_RX 8 |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_RX_TUNE 6 |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_SLEEP 1 |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_SPI_ACTIVE 2 |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_TX 7 |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_ENUM_TX_TUNE 5 |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_INDEX 7 |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_LSB 0 |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_MASK 0x0F |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_MSB 3 |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_SIZE 4 |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_TYPE bitfield |
| #define SI446X_CMD_START_RX_ARG_RXINVALID_STATE_value (((cmd.arg.RAW[7]&0xF))) |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_NOCHANGE 0 |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_READY 3 |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_READY2 4 |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_RX 8 |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_RX_TUNE 6 |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_SLEEP 1 |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_SPI_ACTIVE 2 |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_TX 7 |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_ENUM_TX_TUNE 5 |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_INDEX 5 |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_LSB 0 |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_MASK 0x0F |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_MSB 3 |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_SIZE 4 |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_TYPE bitfield |
| #define SI446X_CMD_START_RX_ARG_RXTIMEOUT_STATE_value (((cmd.arg.RAW[5]&0xF))) |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_ENUM_NOCHANGE 0 |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_ENUM_READY 3 |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_ENUM_READY2 4 |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_ENUM_RX 8 |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_ENUM_RX_TUNE 6 |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_ENUM_SLEEP 1 |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_ENUM_SPI_ACTIVE 2 |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_ENUM_TX 7 |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_ENUM_TX_TUNE 5 |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_INDEX 6 |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_LSB 0 |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_MASK 0x0F |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_MSB 3 |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_SIZE 4 |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_TYPE bitfield |
| #define SI446X_CMD_START_RX_ARG_RXVALID_STATE_value (((cmd.arg.RAW[6]&0xF))) |
| #define SI446X_CMD_START_RX_ARG_START_BIT 0x01 |
| #define SI446X_CMD_START_RX_ARG_START_INDEX 2 |
| #define SI446X_CMD_START_RX_ARG_START_is_true (cmd.arg.RAW[2]&0x1) |
| #define SI446X_CMD_START_RX_ARG_START_LSB 0 |
| #define SI446X_CMD_START_RX_ARG_START_MASK 0x01 |
| #define SI446X_CMD_START_RX_ARG_START_MSB 0 |
| #define SI446X_CMD_START_RX_ARG_START_SIZE 1 |
| #define SI446X_CMD_START_RX_ARG_START_TYPE bitfield |
| #define SI446X_CMD_START_RX_ARG_START_value (((cmd.arg.RAW[2]&0x1))) |
| #define SI446X_CMD_START_TX_ARG_CHANNEL_INDEX 1 |
| #define SI446X_CMD_START_TX_ARG_CHANNEL_LSB 0 |
| #define SI446X_CMD_START_TX_ARG_CHANNEL_MASK 0xFF |
| #define SI446X_CMD_START_TX_ARG_CHANNEL_MAX 255 |
| #define SI446X_CMD_START_TX_ARG_CHANNEL_MIN 0 |
| #define SI446X_CMD_START_TX_ARG_CHANNEL_MSB 7 |
| #define SI446X_CMD_START_TX_ARG_CHANNEL_SIZE 8 |
| #define SI446X_CMD_START_TX_ARG_CHANNEL_TYPE u8 |
| #define SI446X_CMD_START_TX_ARG_CHANNEL_value (((cmd.arg.RAW[1]))) |
| #define SI446X_CMD_START_TX_ARG_CONDITION_INDEX 2 |
| #define SI446X_CMD_START_TX_ARG_CONDITION_LSB 0 |
| #define SI446X_CMD_START_TX_ARG_CONDITION_MASK 0xFF |
| #define SI446X_CMD_START_TX_ARG_CONDITION_MSB 7 |
| #define SI446X_CMD_START_TX_ARG_CONDITION_SIZE 8 |
| #define SI446X_CMD_START_TX_ARG_CONDITION_TYPE bitfield |
| #define SI446X_CMD_START_TX_ARG_CONDITION_value (((cmd.arg.RAW[2]))) |
| #define SI446X_CMD_START_TX_ARG_RETRANSMIT_BIT 0x04 |
| #define SI446X_CMD_START_TX_ARG_RETRANSMIT_INDEX 2 |
| #define SI446X_CMD_START_TX_ARG_RETRANSMIT_is_true (cmd.arg.RAW[2]&0x4) |
| #define SI446X_CMD_START_TX_ARG_RETRANSMIT_LSB 2 |
| #define SI446X_CMD_START_TX_ARG_RETRANSMIT_MASK 0x04 |
| #define SI446X_CMD_START_TX_ARG_RETRANSMIT_MSB 2 |
| #define SI446X_CMD_START_TX_ARG_RETRANSMIT_SIZE 1 |
| #define SI446X_CMD_START_TX_ARG_RETRANSMIT_TYPE bitfield |
| #define SI446X_CMD_START_TX_ARG_RETRANSMIT_value (((cmd.arg.RAW[2]&0x4))>>2) |
| #define SI446X_CMD_START_TX_ARG_START_ENUM_IMMEDIATE 0 |
| #define SI446X_CMD_START_TX_ARG_START_ENUM_UPDATE 3 |
| #define SI446X_CMD_START_TX_ARG_START_ENUM_WUT 1 |
| #define SI446X_CMD_START_TX_ARG_START_INDEX 2 |
| #define SI446X_CMD_START_TX_ARG_START_LSB 0 |
| #define SI446X_CMD_START_TX_ARG_START_MASK 0x03 |
| #define SI446X_CMD_START_TX_ARG_START_MSB 1 |
| #define SI446X_CMD_START_TX_ARG_START_SIZE 2 |
| #define SI446X_CMD_START_TX_ARG_START_TYPE bitfield |
| #define SI446X_CMD_START_TX_ARG_START_value (((cmd.arg.RAW[2]&0x3))) |
| #define SI446X_CMD_START_TX_ARG_TX_DELAY_INDEX 5 |
| #define SI446X_CMD_START_TX_ARG_TX_DELAY_LSB 0 |
| #define SI446X_CMD_START_TX_ARG_TX_DELAY_MASK 0xFF |
| #define SI446X_CMD_START_TX_ARG_TX_DELAY_MAX 128 |
| #define SI446X_CMD_START_TX_ARG_TX_DELAY_MIN 0 |
| #define SI446X_CMD_START_TX_ARG_TX_DELAY_MSB 7 |
| #define SI446X_CMD_START_TX_ARG_TX_DELAY_SIZE 8 |
| #define SI446X_CMD_START_TX_ARG_TX_DELAY_TYPE u8 |
| #define SI446X_CMD_START_TX_ARG_TX_DELAY_value (((cmd.arg.RAW[5]))) |
| #define SI446X_CMD_START_TX_ARG_TX_LEN_INDEX 3 |
| #define SI446X_CMD_START_TX_ARG_TX_LEN_LSB 0 |
| #define SI446X_CMD_START_TX_ARG_TX_LEN_MASK 0xFFFF |
| #define SI446X_CMD_START_TX_ARG_TX_LEN_MAX 8191 |
| #define SI446X_CMD_START_TX_ARG_TX_LEN_MIN 0 |
| #define SI446X_CMD_START_TX_ARG_TX_LEN_MSB 15 |
| #define SI446X_CMD_START_TX_ARG_TX_LEN_SIZE 16 |
| #define SI446X_CMD_START_TX_ARG_TX_LEN_TYPE u16 |
| #define SI446X_CMD_START_TX_ARG_TX_LEN_value (((cmd.arg.RAW_u16[1]))) |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_NOCHANGE 0 |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_READY 3 |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_READY2 4 |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_RX 8 |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_RX_TUNE 6 |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_SLEEP 1 |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_SPI_ACTIVE 2 |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_TX 7 |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_ENUM_TX_TUNE 5 |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_INDEX 2 |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_LSB 4 |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_MASK 0xF0 |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_MSB 7 |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_SIZE 4 |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_TYPE bitfield |
| #define SI446X_CMD_START_TX_ARG_TXCOMPLETE_STATE_value (((cmd.arg.RAW[2]&0xF0))>>4) |
| #define SI446X_CMD_WRITE_TX_FIFO_ARG_FIRST_BYTE_INDEX 1 |
| #define SI446X_CMD_WRITE_TX_FIFO_ARG_FIRST_BYTE_LSB 0 |
| #define SI446X_CMD_WRITE_TX_FIFO_ARG_FIRST_BYTE_MASK 0xFF |
| #define SI446X_CMD_WRITE_TX_FIFO_ARG_FIRST_BYTE_MSB 7 |
| #define SI446X_CMD_WRITE_TX_FIFO_ARG_FIRST_BYTE_SIZE 8 |
| #define SI446X_CMD_WRITE_TX_FIFO_ARG_FIRST_BYTE_TYPE u8 |
| #define SI446X_CMD_WRITE_TX_FIFO_ARG_FIRST_BYTE_value (((cmd.arg.RAW[1]))) |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_CHANNEL_STEP_SIZE_0_LSB 0 |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_CHANNEL_STEP_SIZE_0_MASK 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_CHANNEL_STEP_SIZE_0_MAX 255 |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_CHANNEL_STEP_SIZE_0_MIN 0 |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_CHANNEL_STEP_SIZE_0_MSB 7 |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_CHANNEL_STEP_SIZE_0_SIZE 8 |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_DEFAULT 0x00 |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0_MASK 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_CHANNEL_STEP_SIZE_1_LSB 0 |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_CHANNEL_STEP_SIZE_1_MASK 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_CHANNEL_STEP_SIZE_1_MAX 255 |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_CHANNEL_STEP_SIZE_1_MIN 0 |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_CHANNEL_STEP_SIZE_1_MSB 7 |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_CHANNEL_STEP_SIZE_1_SIZE 8 |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_DEFAULT 0x00 |
| #define SI446X_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1_MASK 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_0_DEFAULT 0x00 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_0_FRAC_0_LSB 0 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_0_FRAC_0_MASK 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_0_FRAC_0_MAX 255 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_0_FRAC_0_MIN 0 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_0_FRAC_0_MSB 7 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_0_FRAC_0_SIZE 8 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_0_MASK 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_1_DEFAULT 0x00 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_1_FRAC_1_LSB 0 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_1_FRAC_1_MASK 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_1_FRAC_1_MAX 255 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_1_FRAC_1_MIN 0 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_1_FRAC_1_MSB 7 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_1_FRAC_1_SIZE 8 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_1_MASK 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_2_DEFAULT 0x08 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_2_FRAC_2_LSB 0 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_2_FRAC_2_MASK 0x7 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_2_FRAC_2_MAX 7 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_2_FRAC_2_MIN 0 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_2_FRAC_2_MSB 2 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_2_FRAC_2_SIZE 3 |
| #define SI446X_PROP_FREQ_CONTROL_FRAC_2_MASK 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_INTE_DEFAULT 0x3C |
| #define SI446X_PROP_FREQ_CONTROL_INTE_INTE_LSB 0 |
| #define SI446X_PROP_FREQ_CONTROL_INTE_INTE_MASK 0x7F |
| #define SI446X_PROP_FREQ_CONTROL_INTE_INTE_MAX 127 |
| #define SI446X_PROP_FREQ_CONTROL_INTE_INTE_MIN 0 |
| #define SI446X_PROP_FREQ_CONTROL_INTE_INTE_MSB 6 |
| #define SI446X_PROP_FREQ_CONTROL_INTE_INTE_SIZE 7 |
| #define SI446X_PROP_FREQ_CONTROL_INTE_MASK 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_DEFAULT 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_MASK 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_VCOCNT_RX_ADJ_LSB 0 |
| #define SI446X_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_VCOCNT_RX_ADJ_MASK 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_VCOCNT_RX_ADJ_MAX 127 |
| #define SI446X_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_VCOCNT_RX_ADJ_MIN -128 |
| #define SI446X_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_VCOCNT_RX_ADJ_MSB 7 |
| #define SI446X_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ_VCOCNT_RX_ADJ_SIZE 8 |
| #define SI446X_PROP_FREQ_CONTROL_W_SIZE_DEFAULT 0x20 |
| #define SI446X_PROP_FREQ_CONTROL_W_SIZE_MASK 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_W_SIZE_W_SIZE_LSB 0 |
| #define SI446X_PROP_FREQ_CONTROL_W_SIZE_W_SIZE_MASK 0xFF |
| #define SI446X_PROP_FREQ_CONTROL_W_SIZE_W_SIZE_MAX 255 |
| #define SI446X_PROP_FREQ_CONTROL_W_SIZE_W_SIZE_MIN 0 |
| #define SI446X_PROP_FREQ_CONTROL_W_SIZE_W_SIZE_MSB 7 |
| #define SI446X_PROP_FREQ_CONTROL_W_SIZE_W_SIZE_SIZE 8 |
| #define SI446X_PROP_FRR_CTL_A_MODE_DEFAULT 0x01 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_CURRENT_STATE 9 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_DISABLED 0 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_CHIP_PEND 8 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_CHIP_STATUS 7 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_MODEM_PEND 6 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_MODEM_STATUS 5 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_PEND 2 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_PH_PEND 4 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_PH_STATUS 3 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_INT_STATUS 1 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_LATCHED_RSSI 10 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_SPARE0 11 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_SPARE1 12 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_SPARE2 13 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_SPARE3 14 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_SPARE4 15 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_SPARE5 16 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_ENUM_SPARE6 17 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_LSB 0 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_MASK 0xFF |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_MSB 7 |
| #define SI446X_PROP_FRR_CTL_A_MODE_FRR_A_MODE_SIZE 8 |
| #define SI446X_PROP_FRR_CTL_A_MODE_MASK 0xFF |
| #define SI446X_PROP_FRR_CTL_B_MODE_DEFAULT 0x02 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_CURRENT_STATE 9 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_DISABLED 0 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_CHIP_PEND 8 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_CHIP_STATUS 7 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_MODEM_PEND 6 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_MODEM_STATUS 5 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_PEND 2 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_PH_PEND 4 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_PH_STATUS 3 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_INT_STATUS 1 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_LATCHED_RSSI 10 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_SPARE0 11 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_SPARE1 12 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_SPARE2 13 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_SPARE3 14 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_SPARE4 15 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_SPARE5 16 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_ENUM_SPARE6 17 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_LSB 0 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_MASK 0xFF |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_MSB 7 |
| #define SI446X_PROP_FRR_CTL_B_MODE_FRR_B_MODE_SIZE 8 |
| #define SI446X_PROP_FRR_CTL_B_MODE_MASK 0xFF |
| #define SI446X_PROP_FRR_CTL_C_MODE_DEFAULT 0x09 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_CURRENT_STATE 9 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_DISABLED 0 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_CHIP_PEND 8 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_CHIP_STATUS 7 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_MODEM_PEND 6 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_MODEM_STATUS 5 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_PEND 2 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_PH_PEND 4 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_PH_STATUS 3 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_INT_STATUS 1 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_LATCHED_RSSI 10 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_SPARE0 11 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_SPARE1 12 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_SPARE2 13 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_SPARE3 14 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_SPARE4 15 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_SPARE5 16 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_ENUM_SPARE6 17 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_LSB 0 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_MASK 0xFF |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_MSB 7 |
| #define SI446X_PROP_FRR_CTL_C_MODE_FRR_C_MODE_SIZE 8 |
| #define SI446X_PROP_FRR_CTL_C_MODE_MASK 0xFF |
| #define SI446X_PROP_FRR_CTL_D_MODE_DEFAULT 0x00 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_CURRENT_STATE 9 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_DISABLED 0 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_INT_CHIP_PEND 8 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_INT_CHIP_STATUS 7 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_INT_MODEM_PEND 6 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_INT_MODEM_STATUS 5 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_INT_PEND 2 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_INT_PH_PEND 4 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_INT_PH_STATUS 3 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_INT_STATUS 1 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_LATCHED_RSSI 10 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_SPARE0 11 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_SPARE1 12 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_SPARE2 13 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_SPARE3 14 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_SPARE4 15 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_SPARE5 16 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_ENUM_SPARE6 17 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_LSB 0 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_MASK 0xFF |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_MSB 7 |
| #define SI446X_PROP_FRR_CTL_D_MODE_FRR_A_MODE_SIZE 8 |
| #define SI446X_PROP_FRR_CTL_D_MODE_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_CLK_CFG_CLK_32K_SEL_ENUM_CRYSTAL 2 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_CLK_32K_SEL_ENUM_OFF 0 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_CLK_32K_SEL_ENUM_RC 1 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_CLK_32K_SEL_LSB 0 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_CLK_32K_SEL_MASK 0x7 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_CLK_32K_SEL_MSB 2 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_CLK_32K_SEL_SIZE 3 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DEFAULT 0 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_EN_BIT 0x40 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_EN_ENUM_DISABLE 0 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_EN_ENUM_ENABLE 1 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_EN_LSB 6 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_EN_MASK 0x40 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_EN_MSB 6 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_EN_SIZE 1 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_SEL_ENUM_DIV_1 0 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_SEL_ENUM_DIV_10 4 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_SEL_ENUM_DIV_15 5 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_SEL_ENUM_DIV_2 1 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_SEL_ENUM_DIV_3 2 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_SEL_ENUM_DIV_30 6 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_SEL_ENUM_DIV_7_5 3 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_SEL_LSB 3 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_SEL_MASK 0x38 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_SEL_MSB 5 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_DIVIDED_CLK_SEL_SIZE 3 |
| #define SI446X_PROP_GLOBAL_CLK_CFG_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_CONFIG_DEFAULT 0x20 |
| #define SI446X_PROP_GLOBAL_CONFIG_FIFO_MODE_BIT 0x10 |
| #define SI446X_PROP_GLOBAL_CONFIG_FIFO_MODE_ENUM_HALF_DUPLEX_FIFO 1 |
| #define SI446X_PROP_GLOBAL_CONFIG_FIFO_MODE_ENUM_SPLIT_FIFO 0 |
| #define SI446X_PROP_GLOBAL_CONFIG_FIFO_MODE_LSB 4 |
| #define SI446X_PROP_GLOBAL_CONFIG_FIFO_MODE_MASK 0x10 |
| #define SI446X_PROP_GLOBAL_CONFIG_FIFO_MODE_MSB 4 |
| #define SI446X_PROP_GLOBAL_CONFIG_FIFO_MODE_SIZE 1 |
| #define SI446X_PROP_GLOBAL_CONFIG_LPF_SATURATION_MODE_BIT 0x40 |
| #define SI446X_PROP_GLOBAL_CONFIG_LPF_SATURATION_MODE_ENUM_HIGH_SAT 0 |
| #define SI446X_PROP_GLOBAL_CONFIG_LPF_SATURATION_MODE_ENUM_LOW_SAT 1 |
| #define SI446X_PROP_GLOBAL_CONFIG_LPF_SATURATION_MODE_LSB 6 |
| #define SI446X_PROP_GLOBAL_CONFIG_LPF_SATURATION_MODE_MASK 0x40 |
| #define SI446X_PROP_GLOBAL_CONFIG_LPF_SATURATION_MODE_MSB 6 |
| #define SI446X_PROP_GLOBAL_CONFIG_LPF_SATURATION_MODE_SIZE 1 |
| #define SI446X_PROP_GLOBAL_CONFIG_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_CONFIG_POWER_MODE_BIT 0x1 |
| #define SI446X_PROP_GLOBAL_CONFIG_POWER_MODE_ENUM_HIGH_POWER 0 |
| #define SI446X_PROP_GLOBAL_CONFIG_POWER_MODE_ENUM_LOW_POWER 1 |
| #define SI446X_PROP_GLOBAL_CONFIG_POWER_MODE_LSB 0 |
| #define SI446X_PROP_GLOBAL_CONFIG_POWER_MODE_MASK 0x1 |
| #define SI446X_PROP_GLOBAL_CONFIG_POWER_MODE_MSB 0 |
| #define SI446X_PROP_GLOBAL_CONFIG_POWER_MODE_SIZE 1 |
| #define SI446X_PROP_GLOBAL_CONFIG_PROTOCOL_LSB 1 |
| #define SI446X_PROP_GLOBAL_CONFIG_PROTOCOL_MASK 0xE |
| #define SI446X_PROP_GLOBAL_CONFIG_PROTOCOL_MSB 3 |
| #define SI446X_PROP_GLOBAL_CONFIG_PROTOCOL_SIZE 3 |
| #define SI446X_PROP_GLOBAL_CONFIG_SEQUENCER_MODE_BIT 0x20 |
| #define SI446X_PROP_GLOBAL_CONFIG_SEQUENCER_MODE_ENUM_FAST 1 |
| #define SI446X_PROP_GLOBAL_CONFIG_SEQUENCER_MODE_ENUM_GUARANTEED 0 |
| #define SI446X_PROP_GLOBAL_CONFIG_SEQUENCER_MODE_LSB 5 |
| #define SI446X_PROP_GLOBAL_CONFIG_SEQUENCER_MODE_MASK 0x20 |
| #define SI446X_PROP_GLOBAL_CONFIG_SEQUENCER_MODE_MSB 5 |
| #define SI446X_PROP_GLOBAL_CONFIG_SEQUENCER_MODE_SIZE 1 |
| #define SI446X_PROP_GLOBAL_LOW_BATT_THRESH_DEFAULT 0x18 |
| #define SI446X_PROP_GLOBAL_LOW_BATT_THRESH_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_LOW_BATT_THRESH_THRESHOLD_ENUM_HIGH_POWER 0 |
| #define SI446X_PROP_GLOBAL_LOW_BATT_THRESH_THRESHOLD_ENUM_LOW_POWER 31 |
| #define SI446X_PROP_GLOBAL_LOW_BATT_THRESH_THRESHOLD_LSB 0 |
| #define SI446X_PROP_GLOBAL_LOW_BATT_THRESH_THRESHOLD_MASK 0x1F |
| #define SI446X_PROP_GLOBAL_LOW_BATT_THRESH_THRESHOLD_MAX 31 |
| #define SI446X_PROP_GLOBAL_LOW_BATT_THRESH_THRESHOLD_MIN 0 |
| #define SI446X_PROP_GLOBAL_LOW_BATT_THRESH_THRESHOLD_MSB 4 |
| #define SI446X_PROP_GLOBAL_LOW_BATT_THRESH_THRESHOLD_SIZE 5 |
| #define SI446X_PROP_GLOBAL_WUT_CAL_DEFAULT 0x00 |
| #define SI446X_PROP_GLOBAL_WUT_CAL_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_WUT_CAL_WUT_CAL_LSB 0 |
| #define SI446X_PROP_GLOBAL_WUT_CAL_WUT_CAL_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_WUT_CAL_WUT_CAL_MAX 255 |
| #define SI446X_PROP_GLOBAL_WUT_CAL_WUT_CAL_MIN 1 |
| #define SI446X_PROP_GLOBAL_WUT_CAL_WUT_CAL_MSB 7 |
| #define SI446X_PROP_GLOBAL_WUT_CAL_WUT_CAL_SIZE 8 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_CAL_EN_BIT 0x1 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_CAL_EN_ENUM_DISABLE_CAL 0 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_CAL_EN_ENUM_ENABLE_CAL 1 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_CAL_EN_LSB 0 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_CAL_EN_MASK 0x1 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_CAL_EN_MSB 0 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_CAL_EN_SIZE 1 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_CAL_PERIOD_ENUM_128_SEC 7 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_CAL_PERIOD_ENUM_16_SEC 4 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_CAL_PERIOD_ENUM_1_SEC 0 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_CAL_PERIOD_ENUM_2_SEC 1 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_CAL_PERIOD_ENUM_32_SEC 5 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_CAL_PERIOD_ENUM_4_SEC 2 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_CAL_PERIOD_ENUM_64_SEC 6 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_CAL_PERIOD_ENUM_8_SEC 3 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_CAL_PERIOD_LSB 3 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_CAL_PERIOD_MASK 0x38 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_CAL_PERIOD_MSB 5 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_CAL_PERIOD_SIZE 3 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_EN_BIT 0x2 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_EN_ENUM_DISABLE_WUT 0 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_EN_ENUM_ENABLE_WUT 1 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_EN_LSB 1 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_EN_MASK 0x2 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_EN_MSB 1 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_EN_SIZE 1 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_LBD_EN_BIT 0x4 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_LBD_EN_ENUM_DISABLE_LBD 0 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_LBD_EN_ENUM_ENABLE_LBD 1 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_LBD_EN_LSB 2 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_LBD_EN_MASK 0x4 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_LBD_EN_MSB 2 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_LBD_EN_SIZE 1 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_LDC_EN_ENUM_DISABLE_LDC 0 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_LDC_EN_ENUM_RX_LDC 1 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_LDC_EN_ENUM_TX_LDC 2 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_LDC_EN_LSB 6 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_LDC_EN_MASK 0xC0 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_LDC_EN_MSB 7 |
| #define SI446X_PROP_GLOBAL_WUT_CONFIG_WUT_LDC_EN_SIZE 2 |
| #define SI446X_PROP_GLOBAL_WUT_LDC_DEFAULT 0x00 |
| #define SI446X_PROP_GLOBAL_WUT_LDC_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_WUT_LDC_WUT_LDC_LSB 0 |
| #define SI446X_PROP_GLOBAL_WUT_LDC_WUT_LDC_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_WUT_LDC_WUT_LDC_MSB 7 |
| #define SI446X_PROP_GLOBAL_WUT_LDC_WUT_LDC_SIZE 8 |
| #define SI446X_PROP_GLOBAL_WUT_M_15_8_DEFAULT 0x00 |
| #define SI446X_PROP_GLOBAL_WUT_M_15_8_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_WUT_M_15_8_WUT_M_15_8_LSB 0 |
| #define SI446X_PROP_GLOBAL_WUT_M_15_8_WUT_M_15_8_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_WUT_M_15_8_WUT_M_15_8_MAX 255 |
| #define SI446X_PROP_GLOBAL_WUT_M_15_8_WUT_M_15_8_MIN 0 |
| #define SI446X_PROP_GLOBAL_WUT_M_15_8_WUT_M_15_8_MSB 7 |
| #define SI446X_PROP_GLOBAL_WUT_M_15_8_WUT_M_15_8_SIZE 8 |
| #define SI446X_PROP_GLOBAL_WUT_M_7_0_DEFAULT 0x01 |
| #define SI446X_PROP_GLOBAL_WUT_M_7_0_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_WUT_M_7_0_WUT_M_7_0_LSB 0 |
| #define SI446X_PROP_GLOBAL_WUT_M_7_0_WUT_M_7_0_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_WUT_M_7_0_WUT_M_7_0_MAX 255 |
| #define SI446X_PROP_GLOBAL_WUT_M_7_0_WUT_M_7_0_MIN 1 |
| #define SI446X_PROP_GLOBAL_WUT_M_7_0_WUT_M_7_0_MSB 7 |
| #define SI446X_PROP_GLOBAL_WUT_M_7_0_WUT_M_7_0_SIZE 8 |
| #define SI446X_PROP_GLOBAL_WUT_R_DEFAULT 0x60 |
| #define SI446X_PROP_GLOBAL_WUT_R_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_WUT_R_WUT_R_LSB 0 |
| #define SI446X_PROP_GLOBAL_WUT_R_WUT_R_MASK 0x1F |
| #define SI446X_PROP_GLOBAL_WUT_R_WUT_R_MAX 20 |
| #define SI446X_PROP_GLOBAL_WUT_R_WUT_R_MIN 0 |
| #define SI446X_PROP_GLOBAL_WUT_R_WUT_R_MSB 4 |
| #define SI446X_PROP_GLOBAL_WUT_R_WUT_R_SIZE 5 |
| #define SI446X_PROP_GLOBAL_WUT_R_WUT_SLEEP_BIT 0x20 |
| #define SI446X_PROP_GLOBAL_WUT_R_WUT_SLEEP_ENUM_READY 0 |
| #define SI446X_PROP_GLOBAL_WUT_R_WUT_SLEEP_ENUM_SLEEP 1 |
| #define SI446X_PROP_GLOBAL_WUT_R_WUT_SLEEP_LSB 5 |
| #define SI446X_PROP_GLOBAL_WUT_R_WUT_SLEEP_MASK 0x20 |
| #define SI446X_PROP_GLOBAL_WUT_R_WUT_SLEEP_MSB 5 |
| #define SI446X_PROP_GLOBAL_WUT_R_WUT_SLEEP_SIZE 1 |
| #define SI446X_PROP_GLOBAL_XO_TUNE_DEFAULT 0x40 |
| #define SI446X_PROP_GLOBAL_XO_TUNE_MASK 0xFF |
| #define SI446X_PROP_GLOBAL_XO_TUNE_TUNE_VALUE_ENUM_FASTEST_FREQUENCY 0 |
| #define SI446X_PROP_GLOBAL_XO_TUNE_TUNE_VALUE_ENUM_SLOWEST_FREQUENCY 127 |
| #define SI446X_PROP_GLOBAL_XO_TUNE_TUNE_VALUE_LSB 0 |
| #define SI446X_PROP_GLOBAL_XO_TUNE_TUNE_VALUE_MASK 0x7F |
| #define SI446X_PROP_GLOBAL_XO_TUNE_TUNE_VALUE_MSB 6 |
| #define SI446X_PROP_GLOBAL_XO_TUNE_TUNE_VALUE_SIZE 7 |
| #define SI446X_PROP_GRP_ID_FREQ_CONTROL 64 |
| #define SI446X_PROP_GRP_ID_FRR_CTL 2 |
| #define SI446X_PROP_GRP_ID_GLOBAL 0 |
| #define SI446X_PROP_GRP_ID_INT_CTL 1 |
| #define SI446X_PROP_GRP_ID_MATCH 48 |
| #define SI446X_PROP_GRP_ID_MODEM 32 |
| #define SI446X_PROP_GRP_ID_MODEM_CHFLT 33 |
| #define SI446X_PROP_GRP_ID_OTP_VARS 242 |
| #define SI446X_PROP_GRP_ID_PA 34 |
| #define SI446X_PROP_GRP_ID_PKT 18 |
| #define SI446X_PROP_GRP_ID_PREAMBLE 16 |
| #define SI446X_PROP_GRP_ID_RX_HOP 80 |
| #define SI446X_PROP_GRP_ID_SYNC 17 |
| #define SI446X_PROP_GRP_ID_SYNTH 35 |
| #define SI446X_PROP_GRP_INDEX_FREQ_CONTROL_CHANNEL_STEP_SIZE_0 5 |
| #define SI446X_PROP_GRP_INDEX_FREQ_CONTROL_CHANNEL_STEP_SIZE_1 4 |
| #define SI446X_PROP_GRP_INDEX_FREQ_CONTROL_FRAC_0 3 |
| #define SI446X_PROP_GRP_INDEX_FREQ_CONTROL_FRAC_1 2 |
| #define SI446X_PROP_GRP_INDEX_FREQ_CONTROL_FRAC_2 1 |
| #define SI446X_PROP_GRP_INDEX_FREQ_CONTROL_INTE 0 |
| #define SI446X_PROP_GRP_INDEX_FREQ_CONTROL_VCOCNT_RX_ADJ 7 |
| #define SI446X_PROP_GRP_INDEX_FREQ_CONTROL_W_SIZE 6 |
| #define SI446X_PROP_GRP_INDEX_FRR_CTL_A_MODE 0 |
| #define SI446X_PROP_GRP_INDEX_FRR_CTL_B_MODE 1 |
| #define SI446X_PROP_GRP_INDEX_FRR_CTL_C_MODE 2 |
| #define SI446X_PROP_GRP_INDEX_FRR_CTL_D_MODE 3 |
| #define SI446X_PROP_GRP_INDEX_GLOBAL_CLK_CFG 1 |
| #define SI446X_PROP_GRP_INDEX_GLOBAL_CONFIG 3 |
| #define SI446X_PROP_GRP_INDEX_GLOBAL_LOW_BATT_THRESH 2 |
| #define SI446X_PROP_GRP_INDEX_GLOBAL_WUT_CAL 9 |
| #define SI446X_PROP_GRP_INDEX_GLOBAL_WUT_CONFIG 4 |
| #define SI446X_PROP_GRP_INDEX_GLOBAL_WUT_LDC 8 |
| #define SI446X_PROP_GRP_INDEX_GLOBAL_WUT_M_15_8 5 |
| #define SI446X_PROP_GRP_INDEX_GLOBAL_WUT_M_7_0 6 |
| #define SI446X_PROP_GRP_INDEX_GLOBAL_WUT_R 7 |
| #define SI446X_PROP_GRP_INDEX_GLOBAL_XO_TUNE 0 |
| #define SI446X_PROP_GRP_INDEX_INT_CTL_CHIP_ENABLE 3 |
| #define SI446X_PROP_GRP_INDEX_INT_CTL_ENABLE 0 |
| #define SI446X_PROP_GRP_INDEX_INT_CTL_MODEM_ENABLE 2 |
| #define SI446X_PROP_GRP_INDEX_INT_CTL_PH_ENABLE 1 |
| #define SI446X_PROP_GRP_INDEX_MATCH_CTRL_1 2 |
| #define SI446X_PROP_GRP_INDEX_MATCH_CTRL_2 5 |
| #define SI446X_PROP_GRP_INDEX_MATCH_CTRL_3 8 |
| #define SI446X_PROP_GRP_INDEX_MATCH_CTRL_4 11 |
| #define SI446X_PROP_GRP_INDEX_MATCH_MASK_1 1 |
| #define SI446X_PROP_GRP_INDEX_MATCH_MASK_2 4 |
| #define SI446X_PROP_GRP_INDEX_MATCH_MASK_3 7 |
| #define SI446X_PROP_GRP_INDEX_MATCH_MASK_4 10 |
| #define SI446X_PROP_GRP_INDEX_MATCH_VALUE_1 0 |
| #define SI446X_PROP_GRP_INDEX_MATCH_VALUE_2 3 |
| #define SI446X_PROP_GRP_INDEX_MATCH_VALUE_3 6 |
| #define SI446X_PROP_GRP_INDEX_MATCH_VALUE_4 9 |
| #define SI446X_PROP_GRP_INDEX_MODEM_ADC_CTRL 52 |
| #define SI446X_PROP_GRP_INDEX_MODEM_AFC_GAIN_0 47 |
| #define SI446X_PROP_GRP_INDEX_MODEM_AFC_GAIN_1 46 |
| #define SI446X_PROP_GRP_INDEX_MODEM_AFC_GEAR 44 |
| #define SI446X_PROP_GRP_INDEX_MODEM_AFC_LIMITER_0 49 |
| #define SI446X_PROP_GRP_INDEX_MODEM_AFC_LIMITER_1 48 |
| #define SI446X_PROP_GRP_INDEX_MODEM_AFC_MISC 50 |
| #define SI446X_PROP_GRP_INDEX_MODEM_AFC_WAIT 45 |
| #define SI446X_PROP_GRP_INDEX_MODEM_AFC_ZIFOFF 51 |
| #define SI446X_PROP_GRP_INDEX_MODEM_AGC_CONTROL 53 |
| #define SI446X_PROP_GRP_INDEX_MODEM_AGC_IFPD_DECAY 58 |
| #define SI446X_PROP_GRP_INDEX_MODEM_AGC_RFPD_DECAY 57 |
| #define SI446X_PROP_GRP_INDEX_MODEM_AGC_WINDOW_SIZE 56 |
| #define SI446X_PROP_GRP_INDEX_MODEM_ANT_DIV_CONTROL 73 |
| #define SI446X_PROP_GRP_INDEX_MODEM_ANT_DIV_MODE 72 |
| #define SI446X_PROP_GRP_INDEX_MODEM_BCR_GAIN_0 40 |
| #define SI446X_PROP_GRP_INDEX_MODEM_BCR_GAIN_1 39 |
| #define SI446X_PROP_GRP_INDEX_MODEM_BCR_GEAR 41 |
| #define SI446X_PROP_GRP_INDEX_MODEM_BCR_MISC0 43 |
| #define SI446X_PROP_GRP_INDEX_MODEM_BCR_MISC1 42 |
| #define SI446X_PROP_GRP_INDEX_MODEM_BCR_NCO_OFFSET_0 38 |
| #define SI446X_PROP_GRP_INDEX_MODEM_BCR_NCO_OFFSET_1 37 |
| #define SI446X_PROP_GRP_INDEX_MODEM_BCR_NCO_OFFSET_2 36 |
| #define SI446X_PROP_GRP_INDEX_MODEM_BCR_OSR_0 35 |
| #define SI446X_PROP_GRP_INDEX_MODEM_BCR_OSR_1 34 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COE0_7_0 13 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COE10_7_0 3 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COE11_7_0 2 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COE12_7_0 1 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COE13_7_0 0 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COE1_7_0 12 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COE2_7_0 11 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COE3_7_0 10 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COE4_7_0 9 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COE5_7_0 8 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COE6_7_0 7 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COE7_7_0 6 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COE8_7_0 5 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COE9_7_0 4 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COEM0 14 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COEM1 15 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COEM2 16 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX1_CHFLT_COEM3 17 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COE0_7_0 31 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COE10_7_0 21 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COE11_7_0 20 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COE12_7_0 19 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COE13_7_0 18 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COE1_7_0 30 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COE2_7_0 29 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COE3_7_0 28 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COE4_7_0 27 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COE5_7_0 26 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COE6_7_0 25 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COE7_7_0 24 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COE8_7_0 23 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COE9_7_0 22 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COEM0 32 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COEM1 33 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COEM2 34 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CHFLT_RX2_CHFLT_COEM3 35 |
| #define SI446X_PROP_GRP_INDEX_MODEM_CLKGEN_BAND 81 |
| #define SI446X_PROP_GRP_INDEX_MODEM_DATA_RATE_0 5 |
| #define SI446X_PROP_GRP_INDEX_MODEM_DATA_RATE_1 4 |
| #define SI446X_PROP_GRP_INDEX_MODEM_DATA_RATE_2 3 |
| #define SI446X_PROP_GRP_INDEX_MODEM_DC_CONTROL 79 |
| #define SI446X_PROP_GRP_INDEX_MODEM_DECIMATION_CFG0 31 |
| #define SI446X_PROP_GRP_INDEX_MODEM_DECIMATION_CFG1 30 |
| #define SI446X_PROP_GRP_INDEX_MODEM_DSM_CTRL 2 |
| #define SI446X_PROP_GRP_INDEX_MODEM_FREQ_DEV_0 12 |
| #define SI446X_PROP_GRP_INDEX_MODEM_FREQ_DEV_1 11 |
| #define SI446X_PROP_GRP_INDEX_MODEM_FREQ_DEV_2 10 |
| #define SI446X_PROP_GRP_INDEX_MODEM_FREQ_OFFSET_0 14 |
| #define SI446X_PROP_GRP_INDEX_MODEM_FREQ_OFFSET_1 13 |
| #define SI446X_PROP_GRP_INDEX_MODEM_FSK4_GAIN0 60 |
| #define SI446X_PROP_GRP_INDEX_MODEM_FSK4_GAIN1 59 |
| #define SI446X_PROP_GRP_INDEX_MODEM_FSK4_MAP 63 |
| #define SI446X_PROP_GRP_INDEX_MODEM_FSK4_TH0 62 |
| #define SI446X_PROP_GRP_INDEX_MODEM_FSK4_TH1 61 |
| #define SI446X_PROP_GRP_INDEX_MODEM_IF_CONTROL 26 |
| #define SI446X_PROP_GRP_INDEX_MODEM_IF_FREQ_0 29 |
| #define SI446X_PROP_GRP_INDEX_MODEM_IF_FREQ_1 28 |
| #define SI446X_PROP_GRP_INDEX_MODEM_IF_FREQ_2 27 |
| #define SI446X_PROP_GRP_INDEX_MODEM_MAP_CONTROL 1 |
| #define SI446X_PROP_GRP_INDEX_MODEM_MDM_CTRL 25 |
| #define SI446X_PROP_GRP_INDEX_MODEM_MOD_TYPE 0 |
| #define SI446X_PROP_GRP_INDEX_MODEM_OOK_BLOPK 65 |
| #define SI446X_PROP_GRP_INDEX_MODEM_OOK_CNT1 66 |
| #define SI446X_PROP_GRP_INDEX_MODEM_OOK_MISC 67 |
| #define SI446X_PROP_GRP_INDEX_MODEM_OOK_PDTC 64 |
| #define SI446X_PROP_GRP_INDEX_MODEM_OOKZEROIF_FDEV_0 33 |
| #define SI446X_PROP_GRP_INDEX_MODEM_OOKZEROIF_FDEV_1 32 |
| #define SI446X_PROP_GRP_INDEX_MODEM_OOKZEROIF_RB_0 80 |
| #define SI446X_PROP_GRP_INDEX_MODEM_OOKZEROIF_RB_1 55 |
| #define SI446X_PROP_GRP_INDEX_MODEM_OOKZEROIF_RB_2 54 |
| #define SI446X_PROP_GRP_INDEX_MODEM_PLL_SETTLE_TIME 83 |
| #define SI446X_PROP_GRP_INDEX_MODEM_RAW_CONTROL 69 |
| #define SI446X_PROP_GRP_INDEX_MODEM_RAW_EYE_0 71 |
| #define SI446X_PROP_GRP_INDEX_MODEM_RAW_EYE_1 70 |
| #define SI446X_PROP_GRP_INDEX_MODEM_RAW_SEARCH 68 |
| #define SI446X_PROP_GRP_INDEX_MODEM_RESERVED_20_52 82 |
| #define SI446X_PROP_GRP_INDEX_MODEM_RSSI_COMP 78 |
| #define SI446X_PROP_GRP_INDEX_MODEM_RSSI_CONTROL 76 |
| #define SI446X_PROP_GRP_INDEX_MODEM_RSSI_CONTROL2 77 |
| #define SI446X_PROP_GRP_INDEX_MODEM_RSSI_JUMP_THRESH 75 |
| #define SI446X_PROP_GRP_INDEX_MODEM_RSSI_THRESH 74 |
| #define SI446X_PROP_GRP_INDEX_MODEM_TX_FILTER_COEFF_0 23 |
| #define SI446X_PROP_GRP_INDEX_MODEM_TX_FILTER_COEFF_1 22 |
| #define SI446X_PROP_GRP_INDEX_MODEM_TX_FILTER_COEFF_2 21 |
| #define SI446X_PROP_GRP_INDEX_MODEM_TX_FILTER_COEFF_3 20 |
| #define SI446X_PROP_GRP_INDEX_MODEM_TX_FILTER_COEFF_4 19 |
| #define SI446X_PROP_GRP_INDEX_MODEM_TX_FILTER_COEFF_5 18 |
| #define SI446X_PROP_GRP_INDEX_MODEM_TX_FILTER_COEFF_6 17 |
| #define SI446X_PROP_GRP_INDEX_MODEM_TX_FILTER_COEFF_7 16 |
| #define SI446X_PROP_GRP_INDEX_MODEM_TX_FILTER_COEFF_8 15 |
| #define SI446X_PROP_GRP_INDEX_MODEM_TX_NCO_MODE_0 9 |
| #define SI446X_PROP_GRP_INDEX_MODEM_TX_NCO_MODE_1 8 |
| #define SI446X_PROP_GRP_INDEX_MODEM_TX_NCO_MODE_2 7 |
| #define SI446X_PROP_GRP_INDEX_MODEM_TX_NCO_MODE_3 6 |
| #define SI446X_PROP_GRP_INDEX_MODEM_TX_RAMP_DELAY 24 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_ADC_VOLTAGE_TRIM 22 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_AUXADC_SY_GAIN_ERROR 20 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_AUXADC_SY_OFFSET_ERROR 21 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_AUXADC_TEMP_INTERCEPT 19 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_AUXADC_TEMP_SLOPE 18 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_BOOT_OSC_CAL 16 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_BOOT_OSC_CAL1 17 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_CAL_ENABLE 7 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_CAL_ENABLE_VTR 6 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_MISC_DELAY 42 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_PH_WATERMARK 38 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_PROC_MON_RCAL 39 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_RC_CAL 13 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_RC_CAL1 14 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_RC_CAL2 15 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_RC_CAL_ADC_TARGET_15_8 11 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_RC_CAL_ADC_TARGET_7_0 12 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_READY_SEQ_DELAY 3 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_REF_CAL_BANDGAP 40 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_REG_ADC_HPF 32 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_REG_ADC_LPF 24 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_REG_CLKGEN_COM_HPF 34 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_REG_CLKGEN_COM_LOW_BAND 30 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_REG_CLKGEN_COM_LPF 26 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_REG_CLKGEN_TX_HPF 36 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_REG_CLKGEN_TX_LPF 28 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_REG_FBDIV_COM_HPF 35 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_REG_FBDIV_COM_LPF 27 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_REG_FBDIV_TX_HPF 37 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_REG_FBDIV_TX_LPF 29 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_REG_RXFE_HPF 31 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_REG_RXFE_LPF 23 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_RX_SEQ_DELAY_15_8 4 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_RX_SEQ_DELAY_7_0 5 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_SPARE0 43 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_SPARE1 44 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_SPI_ACTIVE_SEQ_DELAY_15_8 0 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_SPI_ACTIVE_SEQ_DELAY_7_0 1 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_TX_TUNE_SEQ_DELAY 2 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_VCO_ADJ 41 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_VCO_LOAD5_HPF 33 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_VCO_LOAD5_LPF 25 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_VTR_VCO_LADR_TARGET_VOLTAGE 10 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_VTR_VCO_V1P5_TARGET_VOLTAGE 9 |
| #define SI446X_PROP_GRP_INDEX_OTP_VARS_VTR_VCO_V3P3_TARGET_VOLTAGE 8 |
| #define SI446X_PROP_GRP_INDEX_PA_BIAS_CLKDUTY 2 |
| #define SI446X_PROP_GRP_INDEX_PA_MODE 0 |
| #define SI446X_PROP_GRP_INDEX_PA_PWR_LVL 1 |
| #define SI446X_PROP_GRP_INDEX_PA_RAMP_DOWN_DELAY 5 |
| #define SI446X_PROP_GRP_INDEX_PA_RAMP_EX 4 |
| #define SI446X_PROP_GRP_INDEX_PA_STEP_SIZE 6 |
| #define SI446X_PROP_GRP_INDEX_PA_TC 3 |
| #define SI446X_PROP_GRP_INDEX_PKT_CONFIG1 6 |
| #define SI446X_PROP_GRP_INDEX_PKT_CRC_CONFIG 0 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_1_CONFIG 15 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_1_CRC_CONFIG 16 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_1_LENGTH_12_8 13 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_1_LENGTH_7_0 14 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_2_CONFIG 19 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_2_CRC_CONFIG 20 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_2_LENGTH_12_8 17 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_2_LENGTH_7_0 18 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_3_CONFIG 23 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_3_CRC_CONFIG 24 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_3_LENGTH_12_8 21 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_3_LENGTH_7_0 22 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_4_CONFIG 27 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_4_CRC_CONFIG 28 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_4_LENGTH_12_8 25 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_4_LENGTH_7_0 26 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_5_CONFIG 31 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_5_CRC_CONFIG 32 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_5_LENGTH_12_8 29 |
| #define SI446X_PROP_GRP_INDEX_PKT_FIELD_5_LENGTH_7_0 30 |
| #define SI446X_PROP_GRP_INDEX_PKT_LEN 8 |
| #define SI446X_PROP_GRP_INDEX_PKT_LEN_ADJUST 10 |
| #define SI446X_PROP_GRP_INDEX_PKT_LEN_FIELD_SOURCE 9 |
| #define SI446X_PROP_GRP_INDEX_PKT_RESERVED_18_7 7 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_1_CONFIG 35 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_1_CRC_CONFIG 36 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_1_LENGTH_12_8 33 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_1_LENGTH_7_0 34 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_2_CONFIG 39 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_2_CRC_CONFIG 40 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_2_LENGTH_12_8 37 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_2_LENGTH_7_0 38 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_3_CONFIG 43 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_3_CRC_CONFIG 44 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_3_LENGTH_12_8 41 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_3_LENGTH_7_0 42 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_4_CONFIG 47 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_4_CRC_CONFIG 48 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_4_LENGTH_12_8 45 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_4_LENGTH_7_0 46 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_5_CONFIG 51 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_5_CRC_CONFIG 52 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_5_LENGTH_12_8 49 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_FIELD_5_LENGTH_7_0 50 |
| #define SI446X_PROP_GRP_INDEX_PKT_RX_THRESHOLD 12 |
| #define SI446X_PROP_GRP_INDEX_PKT_TX_THRESHOLD 11 |
| #define SI446X_PROP_GRP_INDEX_PKT_WHT_BIT_NUM 5 |
| #define SI446X_PROP_GRP_INDEX_PKT_WHT_POLY_15_8 1 |
| #define SI446X_PROP_GRP_INDEX_PKT_WHT_POLY_7_0 2 |
| #define SI446X_PROP_GRP_INDEX_PKT_WHT_SEED_15_8 3 |
| #define SI446X_PROP_GRP_INDEX_PKT_WHT_SEED_7_0 4 |
| #define SI446X_PROP_GRP_INDEX_PREAMBLE_CONFIG 4 |
| #define SI446X_PROP_GRP_INDEX_PREAMBLE_CONFIG_NSTD 2 |
| #define SI446X_PROP_GRP_INDEX_PREAMBLE_CONFIG_STD_1 1 |
| #define SI446X_PROP_GRP_INDEX_PREAMBLE_CONFIG_STD_2 3 |
| #define SI446X_PROP_GRP_INDEX_PREAMBLE_PATTERN_15_8 7 |
| #define SI446X_PROP_GRP_INDEX_PREAMBLE_PATTERN_23_16 6 |
| #define SI446X_PROP_GRP_INDEX_PREAMBLE_PATTERN_31_24 5 |
| #define SI446X_PROP_GRP_INDEX_PREAMBLE_PATTERN_7_0 8 |
| #define SI446X_PROP_GRP_INDEX_PREAMBLE_POSTAMBLE_CONFIG 9 |
| #define SI446X_PROP_GRP_INDEX_PREAMBLE_POSTAMBLE_PATTERN_15_8 12 |
| #define SI446X_PROP_GRP_INDEX_PREAMBLE_POSTAMBLE_PATTERN_23_16 11 |
| #define SI446X_PROP_GRP_INDEX_PREAMBLE_POSTAMBLE_PATTERN_31_24 10 |
| #define SI446X_PROP_GRP_INDEX_PREAMBLE_POSTAMBLE_PATTERN_7_0 13 |
| #define SI446X_PROP_GRP_INDEX_PREAMBLE_TX_LENGTH 0 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_CONTROL 0 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_0 2 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_1 3 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_10 12 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_11 13 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_12 14 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_13 15 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_14 16 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_15 17 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_16 18 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_17 19 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_18 20 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_19 21 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_2 4 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_20 22 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_21 23 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_22 24 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_23 25 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_24 26 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_25 27 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_26 28 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_27 29 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_28 30 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_29 31 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_3 5 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_30 32 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_31 33 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_32 34 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_33 35 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_34 36 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_35 37 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_36 38 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_37 39 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_38 40 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_39 41 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_4 6 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_40 42 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_41 43 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_42 44 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_43 45 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_44 46 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_45 47 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_46 48 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_47 49 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_48 50 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_49 51 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_5 7 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_50 52 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_51 53 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_52 54 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_53 55 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_54 56 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_55 57 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_56 58 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_57 59 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_58 60 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_59 61 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_6 8 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_60 62 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_61 63 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_62 64 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_63 65 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_7 9 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_8 10 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_ENTRY_9 11 |
| #define SI446X_PROP_GRP_INDEX_RX_HOP_TABLE_SIZE 1 |
| #define SI446X_PROP_GRP_INDEX_SYNC_BITS_15_8 3 |
| #define SI446X_PROP_GRP_INDEX_SYNC_BITS_23_16 2 |
| #define SI446X_PROP_GRP_INDEX_SYNC_BITS_31_24 1 |
| #define SI446X_PROP_GRP_INDEX_SYNC_BITS_7_0 4 |
| #define SI446X_PROP_GRP_INDEX_SYNC_CONFIG 0 |
| #define SI446X_PROP_GRP_INDEX_SYNTH_LPFILT0 6 |
| #define SI446X_PROP_GRP_INDEX_SYNTH_LPFILT1 5 |
| #define SI446X_PROP_GRP_INDEX_SYNTH_LPFILT2 4 |
| #define SI446X_PROP_GRP_INDEX_SYNTH_LPFILT3 3 |
| #define SI446X_PROP_GRP_INDEX_SYNTH_PFDCP_CPFF 0 |
| #define SI446X_PROP_GRP_INDEX_SYNTH_PFDCP_CPINT 1 |
| #define SI446X_PROP_GRP_INDEX_SYNTH_VCO_KV 2 |
| #define SI446X_PROP_GRP_INDEX_SYNTH_VCO_KVCAL 7 |
| #define SI446X_PROP_GRP_LEN_FREQ_CONTROL 8 |
| #define SI446X_PROP_GRP_LEN_FRR_CTL 4 |
| #define SI446X_PROP_GRP_LEN_GLOBAL 10 |
| #define SI446X_PROP_GRP_LEN_INT_CTL 4 |
| #define SI446X_PROP_GRP_LEN_MATCH 12 |
| #define SI446X_PROP_GRP_LEN_MODEM 84 |
| #define SI446X_PROP_GRP_LEN_MODEM_CHFLT 36 |
| #define SI446X_PROP_GRP_LEN_OTP_VARS 45 |
| #define SI446X_PROP_GRP_LEN_PA 7 |
| #define SI446X_PROP_GRP_LEN_PKT 53 |
| #define SI446X_PROP_GRP_LEN_PREAMBLE 14 |
| #define SI446X_PROP_GRP_LEN_RX_HOP 66 |
| #define SI446X_PROP_GRP_LEN_SYNC 5 |
| #define SI446X_PROP_GRP_LEN_SYNTH 8 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CAL_EN_BIT 0x40 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CAL_EN_LSB 6 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CAL_EN_MASK 0x40 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CAL_EN_MSB 6 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CAL_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CHIP_READY_EN_BIT 0x4 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CHIP_READY_EN_LSB 2 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CHIP_READY_EN_MASK 0x4 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CHIP_READY_EN_MSB 2 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CHIP_READY_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CMD_ERROR_EN_BIT 0x8 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CMD_ERROR_EN_LSB 3 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CMD_ERROR_EN_MASK 0x8 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CMD_ERROR_EN_MSB 3 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_CMD_ERROR_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_DEFAULT 0x04 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_FIFO_UNDERFLOW_OVERFLOW_ERROR_EN_BIT 0x20 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_FIFO_UNDERFLOW_OVERFLOW_ERROR_EN_LSB 5 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_FIFO_UNDERFLOW_OVERFLOW_ERROR_EN_MASK 0x20 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_FIFO_UNDERFLOW_OVERFLOW_ERROR_EN_MSB 5 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_FIFO_UNDERFLOW_OVERFLOW_ERROR_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_LOW_BATT_EN_BIT 0x2 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_LOW_BATT_EN_LSB 1 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_LOW_BATT_EN_MASK 0x2 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_LOW_BATT_EN_MSB 1 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_LOW_BATT_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_MASK 0xFF |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_STATE_CHANGE_EN_BIT 0x10 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_STATE_CHANGE_EN_LSB 4 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_STATE_CHANGE_EN_MASK 0x10 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_STATE_CHANGE_EN_MSB 4 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_STATE_CHANGE_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_WUT_EN_BIT 0x1 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_WUT_EN_LSB 0 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_WUT_EN_MASK 0x1 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_WUT_EN_MSB 0 |
| #define SI446X_PROP_INT_CTL_CHIP_ENABLE_WUT_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_ENABLE_CHIP_INT_STATUS_EN_BIT 0x4 |
| #define SI446X_PROP_INT_CTL_ENABLE_CHIP_INT_STATUS_EN_LSB 2 |
| #define SI446X_PROP_INT_CTL_ENABLE_CHIP_INT_STATUS_EN_MASK 0x4 |
| #define SI446X_PROP_INT_CTL_ENABLE_CHIP_INT_STATUS_EN_MSB 2 |
| #define SI446X_PROP_INT_CTL_ENABLE_CHIP_INT_STATUS_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_ENABLE_DEFAULT 0x04 |
| #define SI446X_PROP_INT_CTL_ENABLE_MASK 0xFF |
| #define SI446X_PROP_INT_CTL_ENABLE_MODEM_INT_STATUS_EN_BIT 0x2 |
| #define SI446X_PROP_INT_CTL_ENABLE_MODEM_INT_STATUS_EN_LSB 1 |
| #define SI446X_PROP_INT_CTL_ENABLE_MODEM_INT_STATUS_EN_MASK 0x2 |
| #define SI446X_PROP_INT_CTL_ENABLE_MODEM_INT_STATUS_EN_MSB 1 |
| #define SI446X_PROP_INT_CTL_ENABLE_MODEM_INT_STATUS_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_ENABLE_PH_INT_STATUS_EN_BIT 0x1 |
| #define SI446X_PROP_INT_CTL_ENABLE_PH_INT_STATUS_EN_LSB 0 |
| #define SI446X_PROP_INT_CTL_ENABLE_PH_INT_STATUS_EN_MASK 0x1 |
| #define SI446X_PROP_INT_CTL_ENABLE_PH_INT_STATUS_EN_MSB 0 |
| #define SI446X_PROP_INT_CTL_ENABLE_PH_INT_STATUS_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_DEFAULT 0x00 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_INVALID_PREAMBLE_EN_BIT 0x4 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_INVALID_PREAMBLE_EN_LSB 2 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_INVALID_PREAMBLE_EN_MASK 0x4 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_INVALID_PREAMBLE_EN_MSB 2 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_INVALID_PREAMBLE_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_INVALID_SYNC_EN_BIT 0x20 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_INVALID_SYNC_EN_LSB 5 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_INVALID_SYNC_EN_MASK 0x20 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_INVALID_SYNC_EN_MSB 5 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_INVALID_SYNC_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_MASK 0xFF |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_POSTAMBLE_DETECT_EN_BIT 0x40 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_POSTAMBLE_DETECT_EN_LSB 6 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_POSTAMBLE_DETECT_EN_MASK 0x40 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_POSTAMBLE_DETECT_EN_MSB 6 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_POSTAMBLE_DETECT_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_PREAMBLE_DETECT_EN_BIT 0x2 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_PREAMBLE_DETECT_EN_LSB 1 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_PREAMBLE_DETECT_EN_MASK 0x2 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_PREAMBLE_DETECT_EN_MSB 1 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_PREAMBLE_DETECT_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_RSSI_EN_BIT 0x8 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_RSSI_EN_LSB 3 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_RSSI_EN_MASK 0x8 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_RSSI_EN_MSB 3 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_RSSI_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_RSSI_JUMP_EN_BIT 0x10 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_RSSI_JUMP_EN_LSB 4 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_RSSI_JUMP_EN_MASK 0x10 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_RSSI_JUMP_EN_MSB 4 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_RSSI_JUMP_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_SYNC_DETECT_EN_BIT 0x1 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_SYNC_DETECT_EN_LSB 0 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_SYNC_DETECT_EN_MASK 0x1 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_SYNC_DETECT_EN_MSB 0 |
| #define SI446X_PROP_INT_CTL_MODEM_ENABLE_SYNC_DETECT_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_CRC_ERROR_EN_BIT 0x8 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_CRC_ERROR_EN_LSB 3 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_CRC_ERROR_EN_MASK 0x8 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_CRC_ERROR_EN_MSB 3 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_CRC_ERROR_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_DEFAULT 0x00 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_FILTER_MATCH_EN_BIT 0x80 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_FILTER_MATCH_EN_LSB 7 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_FILTER_MATCH_EN_MASK 0x80 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_FILTER_MATCH_EN_MSB 7 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_FILTER_MATCH_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_FILTER_MISS_EN_BIT 0x40 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_FILTER_MISS_EN_LSB 6 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_FILTER_MISS_EN_MASK 0x40 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_FILTER_MISS_EN_MSB 6 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_FILTER_MISS_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_MASK 0xFF |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_PACKET_RX_EN_BIT 0x10 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_PACKET_RX_EN_LSB 4 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_PACKET_RX_EN_MASK 0x10 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_PACKET_RX_EN_MSB 4 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_PACKET_RX_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_PACKET_SENT_EN_BIT 0x20 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_PACKET_SENT_EN_LSB 5 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_PACKET_SENT_EN_MASK 0x20 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_PACKET_SENT_EN_MSB 5 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_PACKET_SENT_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_RX_FIFO_ALMOST_FULL_EN_BIT 0x1 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_RX_FIFO_ALMOST_FULL_EN_LSB 0 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_RX_FIFO_ALMOST_FULL_EN_MASK 0x1 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_RX_FIFO_ALMOST_FULL_EN_MSB 0 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_RX_FIFO_ALMOST_FULL_EN_SIZE 1 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_TX_FIFO_ALMOST_EMPTY_EN_BIT 0x2 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_TX_FIFO_ALMOST_EMPTY_EN_LSB 1 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_TX_FIFO_ALMOST_EMPTY_EN_MASK 0x2 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_TX_FIFO_ALMOST_EMPTY_EN_MSB 1 |
| #define SI446X_PROP_INT_CTL_PH_ENABLE_TX_FIFO_ALMOST_EMPTY_EN_SIZE 1 |
| #define SI446X_PROP_MATCH_CTRL_1_DEFAULT 0x00 |
| #define SI446X_PROP_MATCH_CTRL_1_MASK 0xFF |
| #define SI446X_PROP_MATCH_CTRL_1_MATCH_EN_BIT 0x40 |
| #define SI446X_PROP_MATCH_CTRL_1_MATCH_EN_ENUM_MATCH_ENABLE 1 |
| #define SI446X_PROP_MATCH_CTRL_1_MATCH_EN_LSB 6 |
| #define SI446X_PROP_MATCH_CTRL_1_MATCH_EN_MASK 0x40 |
| #define SI446X_PROP_MATCH_CTRL_1_MATCH_EN_MSB 6 |
| #define SI446X_PROP_MATCH_CTRL_1_MATCH_EN_SIZE 1 |
| #define SI446X_PROP_MATCH_CTRL_1_OFFSET_LSB 0 |
| #define SI446X_PROP_MATCH_CTRL_1_OFFSET_MASK 0x1F |
| #define SI446X_PROP_MATCH_CTRL_1_OFFSET_MAX 0x1F |
| #define SI446X_PROP_MATCH_CTRL_1_OFFSET_MIN 0 |
| #define SI446X_PROP_MATCH_CTRL_1_OFFSET_MSB 4 |
| #define SI446X_PROP_MATCH_CTRL_1_OFFSET_SIZE 5 |
| #define SI446X_PROP_MATCH_CTRL_1_POLARITY_BIT 0x80 |
| #define SI446X_PROP_MATCH_CTRL_1_POLARITY_LSB 7 |
| #define SI446X_PROP_MATCH_CTRL_1_POLARITY_MASK 0x80 |
| #define SI446X_PROP_MATCH_CTRL_1_POLARITY_MSB 7 |
| #define SI446X_PROP_MATCH_CTRL_1_POLARITY_SIZE 1 |
| #define SI446X_PROP_MATCH_CTRL_2_DEFAULT 0x00 |
| #define SI446X_PROP_MATCH_CTRL_2_LOGIC_BIT 0x40 |
| #define SI446X_PROP_MATCH_CTRL_2_LOGIC_LSB 6 |
| #define SI446X_PROP_MATCH_CTRL_2_LOGIC_MASK 0x40 |
| #define SI446X_PROP_MATCH_CTRL_2_LOGIC_MSB 6 |
| #define SI446X_PROP_MATCH_CTRL_2_LOGIC_SIZE 1 |
| #define SI446X_PROP_MATCH_CTRL_2_MASK 0xFF |
| #define SI446X_PROP_MATCH_CTRL_2_OFFSET_LSB 0 |
| #define SI446X_PROP_MATCH_CTRL_2_OFFSET_MASK 0x1F |
| #define SI446X_PROP_MATCH_CTRL_2_OFFSET_MAX 0x1F |
| #define SI446X_PROP_MATCH_CTRL_2_OFFSET_MIN 0 |
| #define SI446X_PROP_MATCH_CTRL_2_OFFSET_MSB 4 |
| #define SI446X_PROP_MATCH_CTRL_2_OFFSET_SIZE 5 |
| #define SI446X_PROP_MATCH_CTRL_2_POLARITY_BIT 0x80 |
| #define SI446X_PROP_MATCH_CTRL_2_POLARITY_LSB 7 |
| #define SI446X_PROP_MATCH_CTRL_2_POLARITY_MASK 0x80 |
| #define SI446X_PROP_MATCH_CTRL_2_POLARITY_MSB 7 |
| #define SI446X_PROP_MATCH_CTRL_2_POLARITY_SIZE 1 |
| #define SI446X_PROP_MATCH_CTRL_3_DEFAULT 0x00 |
| #define SI446X_PROP_MATCH_CTRL_3_LOGIC_BIT 0x40 |
| #define SI446X_PROP_MATCH_CTRL_3_LOGIC_LSB 6 |
| #define SI446X_PROP_MATCH_CTRL_3_LOGIC_MASK 0x40 |
| #define SI446X_PROP_MATCH_CTRL_3_LOGIC_MSB 6 |
| #define SI446X_PROP_MATCH_CTRL_3_LOGIC_SIZE 1 |
| #define SI446X_PROP_MATCH_CTRL_3_MASK 0xFF |
| #define SI446X_PROP_MATCH_CTRL_3_OFFSET_LSB 0 |
| #define SI446X_PROP_MATCH_CTRL_3_OFFSET_MASK 0x1F |
| #define SI446X_PROP_MATCH_CTRL_3_OFFSET_MAX 0x1F |
| #define SI446X_PROP_MATCH_CTRL_3_OFFSET_MIN 0 |
| #define SI446X_PROP_MATCH_CTRL_3_OFFSET_MSB 4 |
| #define SI446X_PROP_MATCH_CTRL_3_OFFSET_SIZE 5 |
| #define SI446X_PROP_MATCH_CTRL_3_POLARITY_BIT 0x80 |
| #define SI446X_PROP_MATCH_CTRL_3_POLARITY_LSB 7 |
| #define SI446X_PROP_MATCH_CTRL_3_POLARITY_MASK 0x80 |
| #define SI446X_PROP_MATCH_CTRL_3_POLARITY_MSB 7 |
| #define SI446X_PROP_MATCH_CTRL_3_POLARITY_SIZE 1 |
| #define SI446X_PROP_MATCH_CTRL_4_DEFAULT 0x00 |
| #define SI446X_PROP_MATCH_CTRL_4_LOGIC_BIT 0x40 |
| #define SI446X_PROP_MATCH_CTRL_4_LOGIC_LSB 6 |
| #define SI446X_PROP_MATCH_CTRL_4_LOGIC_MASK 0x40 |
| #define SI446X_PROP_MATCH_CTRL_4_LOGIC_MSB 6 |
| #define SI446X_PROP_MATCH_CTRL_4_LOGIC_SIZE 1 |
| #define SI446X_PROP_MATCH_CTRL_4_MASK 0xFF |
| #define SI446X_PROP_MATCH_CTRL_4_OFFSET_LSB 0 |
| #define SI446X_PROP_MATCH_CTRL_4_OFFSET_MASK 0x1F |
| #define SI446X_PROP_MATCH_CTRL_4_OFFSET_MAX 0x1F |
| #define SI446X_PROP_MATCH_CTRL_4_OFFSET_MIN 0 |
| #define SI446X_PROP_MATCH_CTRL_4_OFFSET_MSB 4 |
| #define SI446X_PROP_MATCH_CTRL_4_OFFSET_SIZE 5 |
| #define SI446X_PROP_MATCH_CTRL_4_POLARITY_BIT 0x80 |
| #define SI446X_PROP_MATCH_CTRL_4_POLARITY_LSB 7 |
| #define SI446X_PROP_MATCH_CTRL_4_POLARITY_MASK 0x80 |
| #define SI446X_PROP_MATCH_CTRL_4_POLARITY_MSB 7 |
| #define SI446X_PROP_MATCH_CTRL_4_POLARITY_SIZE 1 |
| #define SI446X_PROP_MATCH_MASK_1_DEFAULT 0x00 |
| #define SI446X_PROP_MATCH_MASK_1_MASK 0xFF |
| #define SI446X_PROP_MATCH_MASK_1_MASK_1_LSB 0 |
| #define SI446X_PROP_MATCH_MASK_1_MASK_1_MASK 0xFF |
| #define SI446X_PROP_MATCH_MASK_1_MASK_1_MAX 0xFF |
| #define SI446X_PROP_MATCH_MASK_1_MASK_1_MIN 0 |
| #define SI446X_PROP_MATCH_MASK_1_MASK_1_MSB 7 |
| #define SI446X_PROP_MATCH_MASK_1_MASK_1_SIZE 8 |
| #define SI446X_PROP_MATCH_MASK_2_DEFAULT 0x00 |
| #define SI446X_PROP_MATCH_MASK_2_MASK 0xFF |
| #define SI446X_PROP_MATCH_MASK_2_MASK_2_LSB 0 |
| #define SI446X_PROP_MATCH_MASK_2_MASK_2_MASK 0xFF |
| #define SI446X_PROP_MATCH_MASK_2_MASK_2_MAX 0xFF |
| #define SI446X_PROP_MATCH_MASK_2_MASK_2_MIN 0 |
| #define SI446X_PROP_MATCH_MASK_2_MASK_2_MSB 7 |
| #define SI446X_PROP_MATCH_MASK_2_MASK_2_SIZE 8 |
| #define SI446X_PROP_MATCH_MASK_3_DEFAULT 0x00 |
| #define SI446X_PROP_MATCH_MASK_3_MASK 0xFF |
| #define SI446X_PROP_MATCH_MASK_3_MASK_3_LSB 0 |
| #define SI446X_PROP_MATCH_MASK_3_MASK_3_MASK 0xFF |
| #define SI446X_PROP_MATCH_MASK_3_MASK_3_MAX 0xFF |
| #define SI446X_PROP_MATCH_MASK_3_MASK_3_MIN 0 |
| #define SI446X_PROP_MATCH_MASK_3_MASK_3_MSB 7 |
| #define SI446X_PROP_MATCH_MASK_3_MASK_3_SIZE 8 |
| #define SI446X_PROP_MATCH_MASK_4_DEFAULT 0x00 |
| #define SI446X_PROP_MATCH_MASK_4_MASK 0xFF |
| #define SI446X_PROP_MATCH_MASK_4_MASK_4_LSB 0 |
| #define SI446X_PROP_MATCH_MASK_4_MASK_4_MASK 0xFF |
| #define SI446X_PROP_MATCH_MASK_4_MASK_4_MAX 0xFF |
| #define SI446X_PROP_MATCH_MASK_4_MASK_4_MIN 0 |
| #define SI446X_PROP_MATCH_MASK_4_MASK_4_MSB 7 |
| #define SI446X_PROP_MATCH_MASK_4_MASK_4_SIZE 8 |
| #define SI446X_PROP_MATCH_VALUE_1_DEFAULT 0x00 |
| #define SI446X_PROP_MATCH_VALUE_1_MASK 0xFF |
| #define SI446X_PROP_MATCH_VALUE_1_VALUE_1_LSB 0 |
| #define SI446X_PROP_MATCH_VALUE_1_VALUE_1_MASK 0xFF |
| #define SI446X_PROP_MATCH_VALUE_1_VALUE_1_MAX 0xFF |
| #define SI446X_PROP_MATCH_VALUE_1_VALUE_1_MIN 0 |
| #define SI446X_PROP_MATCH_VALUE_1_VALUE_1_MSB 7 |
| #define SI446X_PROP_MATCH_VALUE_1_VALUE_1_SIZE 8 |
| #define SI446X_PROP_MATCH_VALUE_2_DEFAULT 0x00 |
| #define SI446X_PROP_MATCH_VALUE_2_MASK 0xFF |
| #define SI446X_PROP_MATCH_VALUE_2_VALUE_2_LSB 0 |
| #define SI446X_PROP_MATCH_VALUE_2_VALUE_2_MASK 0xFF |
| #define SI446X_PROP_MATCH_VALUE_2_VALUE_2_MAX 0xFF |
| #define SI446X_PROP_MATCH_VALUE_2_VALUE_2_MIN 0 |
| #define SI446X_PROP_MATCH_VALUE_2_VALUE_2_MSB 7 |
| #define SI446X_PROP_MATCH_VALUE_2_VALUE_2_SIZE 8 |
| #define SI446X_PROP_MATCH_VALUE_3_DEFAULT 0x00 |
| #define SI446X_PROP_MATCH_VALUE_3_MASK 0xFF |
| #define SI446X_PROP_MATCH_VALUE_3_VALUE_3_LSB 0 |
| #define SI446X_PROP_MATCH_VALUE_3_VALUE_3_MASK 0xFF |
| #define SI446X_PROP_MATCH_VALUE_3_VALUE_3_MAX 0xFF |
| #define SI446X_PROP_MATCH_VALUE_3_VALUE_3_MIN 0 |
| #define SI446X_PROP_MATCH_VALUE_3_VALUE_3_MSB 7 |
| #define SI446X_PROP_MATCH_VALUE_3_VALUE_3_SIZE 8 |
| #define SI446X_PROP_MATCH_VALUE_4_DEFAULT 0x00 |
| #define SI446X_PROP_MATCH_VALUE_4_MASK 0xFF |
| #define SI446X_PROP_MATCH_VALUE_4_VALUE_4_LSB 0 |
| #define SI446X_PROP_MATCH_VALUE_4_VALUE_4_MASK 0xFF |
| #define SI446X_PROP_MATCH_VALUE_4_VALUE_4_MAX 0xFF |
| #define SI446X_PROP_MATCH_VALUE_4_VALUE_4_MIN 0 |
| #define SI446X_PROP_MATCH_VALUE_4_VALUE_4_MSB 7 |
| #define SI446X_PROP_MATCH_VALUE_4_VALUE_4_SIZE 8 |
| #define SI446X_PROP_MODEM_ADC_CTRL_DEFAULT 0x00 |
| #define SI446X_PROP_MODEM_ADC_CTRL_EN_DRST_BIT 0x8 |
| #define SI446X_PROP_MODEM_ADC_CTRL_EN_DRST_LSB 3 |
| #define SI446X_PROP_MODEM_ADC_CTRL_EN_DRST_MASK 0x8 |
| #define SI446X_PROP_MODEM_ADC_CTRL_EN_DRST_MSB 3 |
| #define SI446X_PROP_MODEM_ADC_CTRL_EN_DRST_SIZE 1 |
| #define SI446X_PROP_MODEM_ADC_CTRL_HGAIN_BIT 0x10 |
| #define SI446X_PROP_MODEM_ADC_CTRL_HGAIN_LSB 4 |
| #define SI446X_PROP_MODEM_ADC_CTRL_HGAIN_MASK 0x10 |
| #define SI446X_PROP_MODEM_ADC_CTRL_HGAIN_MSB 4 |
| #define SI446X_PROP_MODEM_ADC_CTRL_HGAIN_SIZE 1 |
| #define SI446X_PROP_MODEM_ADC_CTRL_MASK 0xFF |
| #define SI446X_PROP_MODEM_ADC_CTRL_REALADC_BIT 0x2 |
| #define SI446X_PROP_MODEM_ADC_CTRL_REALADC_LSB 1 |
| #define SI446X_PROP_MODEM_ADC_CTRL_REALADC_MASK 0x2 |
| #define SI446X_PROP_MODEM_ADC_CTRL_REALADC_MSB 1 |
| #define SI446X_PROP_MODEM_ADC_CTRL_REALADC_SIZE 1 |
| #define SI446X_PROP_MODEM_AFC_GAIN_0_AFCGAIN_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_AFC_GAIN_0_AFCGAIN_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_AFC_GAIN_0_AFCGAIN_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_AFC_GAIN_0_AFCGAIN_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_AFC_GAIN_0_DEFAULT 0x69 |
| #define SI446X_PROP_MODEM_AFC_GAIN_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_AFCBD_BIT 0x40 |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_AFCBD_LSB 6 |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_AFCBD_MASK 0x40 |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_AFCBD_MSB 6 |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_AFCBD_SIZE 1 |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_AFCGAIN_12_8_LSB 0 |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_AFCGAIN_12_8_MASK 0x1F |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_AFCGAIN_12_8_MSB 4 |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_AFCGAIN_12_8_SIZE 5 |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_DEFAULT 0x83 |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_ENAFC_BIT 0x80 |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_ENAFC_LSB 7 |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_ENAFC_MASK 0x80 |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_ENAFC_MSB 7 |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_ENAFC_SIZE 1 |
| #define SI446X_PROP_MODEM_AFC_GAIN_1_MASK 0xFF |
| #define SI446X_PROP_MODEM_AFC_GEAR_AFC_FAST_LSB 3 |
| #define SI446X_PROP_MODEM_AFC_GEAR_AFC_FAST_MASK 0x38 |
| #define SI446X_PROP_MODEM_AFC_GEAR_AFC_FAST_MSB 5 |
| #define SI446X_PROP_MODEM_AFC_GEAR_AFC_FAST_SIZE 3 |
| #define SI446X_PROP_MODEM_AFC_GEAR_AFC_SLOW_LSB 0 |
| #define SI446X_PROP_MODEM_AFC_GEAR_AFC_SLOW_MASK 0x7 |
| #define SI446X_PROP_MODEM_AFC_GEAR_AFC_SLOW_MSB 2 |
| #define SI446X_PROP_MODEM_AFC_GEAR_AFC_SLOW_SIZE 3 |
| #define SI446X_PROP_MODEM_AFC_GEAR_DEFAULT 0x00 |
| #define SI446X_PROP_MODEM_AFC_GEAR_GEAR_SW_LSB 6 |
| #define SI446X_PROP_MODEM_AFC_GEAR_GEAR_SW_MASK 0xC0 |
| #define SI446X_PROP_MODEM_AFC_GEAR_GEAR_SW_MSB 7 |
| #define SI446X_PROP_MODEM_AFC_GEAR_GEAR_SW_SIZE 2 |
| #define SI446X_PROP_MODEM_AFC_GEAR_MASK 0xFF |
| #define SI446X_PROP_MODEM_AFC_LIMITER_0_AFCLIM_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_AFC_LIMITER_0_AFCLIM_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_AFC_LIMITER_0_AFCLIM_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_AFC_LIMITER_0_AFCLIM_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_AFC_LIMITER_0_DEFAULT 0x40 |
| #define SI446X_PROP_MODEM_AFC_LIMITER_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_AFC_LIMITER_1_AFCLIM_14_8_LSB 0 |
| #define SI446X_PROP_MODEM_AFC_LIMITER_1_AFCLIM_14_8_MASK 0x7F |
| #define SI446X_PROP_MODEM_AFC_LIMITER_1_AFCLIM_14_8_MSB 6 |
| #define SI446X_PROP_MODEM_AFC_LIMITER_1_AFCLIM_14_8_SIZE 7 |
| #define SI446X_PROP_MODEM_AFC_LIMITER_1_DEFAULT 0x00 |
| #define SI446X_PROP_MODEM_AFC_LIMITER_1_MASK 0xFF |
| #define SI446X_PROP_MODEM_AFC_MISC_DEFAULT 0xA0 |
| #define SI446X_PROP_MODEM_AFC_MISC_EN2TB_EST_BIT 0x20 |
| #define SI446X_PROP_MODEM_AFC_MISC_EN2TB_EST_LSB 5 |
| #define SI446X_PROP_MODEM_AFC_MISC_EN2TB_EST_MASK 0x20 |
| #define SI446X_PROP_MODEM_AFC_MISC_EN2TB_EST_MSB 5 |
| #define SI446X_PROP_MODEM_AFC_MISC_EN2TB_EST_SIZE 1 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENAFC_CLKSW_BIT 0x8 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENAFC_CLKSW_LSB 3 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENAFC_CLKSW_MASK 0x8 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENAFC_CLKSW_MSB 3 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENAFC_CLKSW_SIZE 1 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENAFCFRZ_BIT 0x80 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENAFCFRZ_LSB 7 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENAFCFRZ_MASK 0x80 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENAFCFRZ_MSB 7 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENAFCFRZ_SIZE 1 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENFBPLL_BIT 0x40 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENFBPLL_LSB 6 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENFBPLL_MASK 0x40 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENFBPLL_MSB 6 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENFBPLL_SIZE 1 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENFZPMEND_BIT 0x10 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENFZPMEND_LSB 4 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENFZPMEND_MASK 0x10 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENFZPMEND_MSB 4 |
| #define SI446X_PROP_MODEM_AFC_MISC_ENFZPMEND_SIZE 1 |
| #define SI446X_PROP_MODEM_AFC_MISC_MASK 0xFF |
| #define SI446X_PROP_MODEM_AFC_MISC_NON_FRZEN_BIT 0x2 |
| #define SI446X_PROP_MODEM_AFC_MISC_NON_FRZEN_LSB 1 |
| #define SI446X_PROP_MODEM_AFC_MISC_NON_FRZEN_MASK 0x2 |
| #define SI446X_PROP_MODEM_AFC_MISC_NON_FRZEN_MSB 1 |
| #define SI446X_PROP_MODEM_AFC_MISC_NON_FRZEN_SIZE 1 |
| #define SI446X_PROP_MODEM_AFC_MISC_OOK_ZEROG_BIT 0x4 |
| #define SI446X_PROP_MODEM_AFC_MISC_OOK_ZEROG_LSB 2 |
| #define SI446X_PROP_MODEM_AFC_MISC_OOK_ZEROG_MASK 0x4 |
| #define SI446X_PROP_MODEM_AFC_MISC_OOK_ZEROG_MSB 2 |
| #define SI446X_PROP_MODEM_AFC_MISC_OOK_ZEROG_SIZE 1 |
| #define SI446X_PROP_MODEM_AFC_WAIT_DEFAULT 0x23 |
| #define SI446X_PROP_MODEM_AFC_WAIT_LGWAIT_LSB 0 |
| #define SI446X_PROP_MODEM_AFC_WAIT_LGWAIT_MASK 0xF |
| #define SI446X_PROP_MODEM_AFC_WAIT_LGWAIT_MSB 3 |
| #define SI446X_PROP_MODEM_AFC_WAIT_LGWAIT_SIZE 4 |
| #define SI446X_PROP_MODEM_AFC_WAIT_MASK 0xFF |
| #define SI446X_PROP_MODEM_AFC_WAIT_SHWAIT_LSB 4 |
| #define SI446X_PROP_MODEM_AFC_WAIT_SHWAIT_MASK 0xF0 |
| #define SI446X_PROP_MODEM_AFC_WAIT_SHWAIT_MSB 7 |
| #define SI446X_PROP_MODEM_AFC_WAIT_SHWAIT_SIZE 4 |
| #define SI446X_PROP_MODEM_AFC_ZIFOFF_DEFAULT 0x00 |
| #define SI446X_PROP_MODEM_AFC_ZIFOFF_MASK 0xFF |
| #define SI446X_PROP_MODEM_AFC_ZIFOFF_ZEROFF_LSB 0 |
| #define SI446X_PROP_MODEM_AFC_ZIFOFF_ZEROFF_MASK 0xFF |
| #define SI446X_PROP_MODEM_AFC_ZIFOFF_ZEROFF_MSB 7 |
| #define SI446X_PROP_MODEM_AFC_ZIFOFF_ZEROFF_SIZE 8 |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_ANT2PM_THD_LSB 4 |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_ANT2PM_THD_MASK 0xF0 |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_ANT2PM_THD_MSB 7 |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_ANT2PM_THD_SIZE 4 |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_ANTDIV_LSB 0 |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_ANTDIV_MASK 0x7 |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_ANTDIV_MSB 2 |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_ANTDIV_SIZE 3 |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_DEFAULT 0x80 |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_MASK 0xFF |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_MATAP_BIT 0x8 |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_MATAP_LSB 3 |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_MATAP_MASK 0x8 |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_MATAP_MSB 3 |
| #define SI446X_PROP_MODEM_ANT_DIV_CONTROL_MATAP_SIZE 1 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE0_7_0_DEFAULT 0xFD |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE0_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE0_7_0_RX1_CHFLT_COE0_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE0_7_0_RX1_CHFLT_COE0_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE0_7_0_RX1_CHFLT_COE0_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE0_7_0_RX1_CHFLT_COE0_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE10_7_0_DEFAULT 0x51 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE10_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE10_7_0_RX1_CHFLT_COE10_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE10_7_0_RX1_CHFLT_COE10_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE10_7_0_RX1_CHFLT_COE10_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE10_7_0_RX1_CHFLT_COE10_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE11_7_0_DEFAULT 0x0F |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE11_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE11_7_0_RX1_CHFLT_COE11_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE11_7_0_RX1_CHFLT_COE11_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE11_7_0_RX1_CHFLT_COE11_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE11_7_0_RX1_CHFLT_COE11_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE12_7_0_DEFAULT 0xBA |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE12_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE12_7_0_RX1_CHFLT_COE12_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE12_7_0_RX1_CHFLT_COE12_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE12_7_0_RX1_CHFLT_COE12_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE12_7_0_RX1_CHFLT_COE12_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_DEFAULT 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_RX1_CHFLT_COE13_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_RX1_CHFLT_COE13_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_RX1_CHFLT_COE13_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_RX1_CHFLT_COE13_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_DEFAULT 0xFC |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_RX1_CHFLT_COE1_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_RX1_CHFLT_COE1_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_RX1_CHFLT_COE1_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_RX1_CHFLT_COE1_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE2_7_0_DEFAULT 0x01 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE2_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE2_7_0_RX1_CHFLT_COE2_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE2_7_0_RX1_CHFLT_COE2_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE2_7_0_RX1_CHFLT_COE2_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE2_7_0_RX1_CHFLT_COE2_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE3_7_0_DEFAULT 0x0F |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE3_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE3_7_0_RX1_CHFLT_COE3_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE3_7_0_RX1_CHFLT_COE3_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE3_7_0_RX1_CHFLT_COE3_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE3_7_0_RX1_CHFLT_COE3_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE4_7_0_DEFAULT 0x1E |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE4_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE4_7_0_RX1_CHFLT_COE4_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE4_7_0_RX1_CHFLT_COE4_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE4_7_0_RX1_CHFLT_COE4_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE4_7_0_RX1_CHFLT_COE4_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE5_7_0_DEFAULT 0x1B |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE5_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE5_7_0_RX1_CHFLT_COE5_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE5_7_0_RX1_CHFLT_COE5_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE5_7_0_RX1_CHFLT_COE5_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE5_7_0_RX1_CHFLT_COE5_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE6_7_0_DEFAULT 0xFC |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE6_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE6_7_0_RX1_CHFLT_COE6_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE6_7_0_RX1_CHFLT_COE6_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE6_7_0_RX1_CHFLT_COE6_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE6_7_0_RX1_CHFLT_COE6_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE7_7_0_DEFAULT 0xC9 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE7_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE7_7_0_RX1_CHFLT_COE7_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE7_7_0_RX1_CHFLT_COE7_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE7_7_0_RX1_CHFLT_COE7_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE7_7_0_RX1_CHFLT_COE7_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE8_7_0_DEFAULT 0xA9 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE8_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE8_7_0_RX1_CHFLT_COE8_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE8_7_0_RX1_CHFLT_COE8_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE8_7_0_RX1_CHFLT_COE8_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE8_7_0_RX1_CHFLT_COE8_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE9_7_0_DEFAULT 0xCF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE9_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE9_7_0_RX1_CHFLT_COE9_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE9_7_0_RX1_CHFLT_COE9_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE9_7_0_RX1_CHFLT_COE9_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COE9_7_0_RX1_CHFLT_COE9_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_DEFAULT 0x15 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE10_9_8_LSB 6 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE10_9_8_MASK 0xC0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE10_9_8_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE10_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE11_9_8_LSB 4 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE11_9_8_MASK 0x30 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE11_9_8_MSB 5 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE11_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE12_9_8_LSB 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE12_9_8_MASK 0xC |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE12_9_8_MSB 3 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE12_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE13_9_8_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE13_9_8_MASK 0x3 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE13_9_8_MSB 1 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM0_RX1COE13_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_DEFAULT 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE6_9_8_LSB 6 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE6_9_8_MASK 0xC0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE6_9_8_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE6_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE7_9_8_LSB 4 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE7_9_8_MASK 0x30 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE7_9_8_MSB 5 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE7_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE8_9_8_LSB 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE8_9_8_MASK 0xC |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE8_9_8_MSB 3 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE8_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE9_9_8_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE9_9_8_MASK 0x3 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE9_9_8_MSB 1 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM1_RX1COE9_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_DEFAULT 0x00 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE2_9_8_LSB 6 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE2_9_8_MASK 0xC0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE2_9_8_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE2_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE3_9_8_LSB 4 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE3_9_8_MASK 0x30 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE3_9_8_MSB 5 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE3_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE4_9_8_LSB 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE4_9_8_MASK 0xC |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE4_9_8_MSB 3 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE4_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE5_9_8_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE5_9_8_MASK 0x3 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE5_9_8_MSB 1 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM2_RX1COE5_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM3_DEFAULT 0x0F |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM3_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM3_RX1COE0_9_8_LSB 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM3_RX1COE0_9_8_MASK 0xC |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM3_RX1COE0_9_8_MSB 3 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM3_RX1COE0_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM3_RX1COE1_9_8_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM3_RX1COE1_9_8_MASK 0x3 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM3_RX1COE1_9_8_MSB 1 |
| #define SI446X_PROP_MODEM_CHFLT_RX1_CHFLT_COEM3_RX1COE1_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE0_7_0_DEFAULT 0x00 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE0_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE0_7_0_RX2_CHFLT_COE0_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE0_7_0_RX2_CHFLT_COE0_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE0_7_0_RX2_CHFLT_COE0_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE0_7_0_RX2_CHFLT_COE0_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE10_7_0_DEFAULT 0x7F |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE10_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE10_7_0_RX2_CHFLT_COE10_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE10_7_0_RX2_CHFLT_COE10_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE10_7_0_RX2_CHFLT_COE10_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE10_7_0_RX2_CHFLT_COE10_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE11_7_0_DEFAULT 0x30 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE11_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE11_7_0_RX2_CHFLT_COE11_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE11_7_0_RX2_CHFLT_COE11_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE11_7_0_RX2_CHFLT_COE11_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE11_7_0_RX2_CHFLT_COE11_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE12_7_0_DEFAULT 0xC4 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE12_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE12_7_0_RX2_CHFLT_COE12_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE12_7_0_RX2_CHFLT_COE12_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE12_7_0_RX2_CHFLT_COE12_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE12_7_0_RX2_CHFLT_COE12_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE13_7_0_DEFAULT 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE13_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE13_7_0_RX2_CHFLT_COE13_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE13_7_0_RX2_CHFLT_COE13_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE13_7_0_RX2_CHFLT_COE13_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE13_7_0_RX2_CHFLT_COE13_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE1_7_0_DEFAULT 0x03 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE1_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE1_7_0_RX2_CHFLT_COE1_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE1_7_0_RX2_CHFLT_COE1_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE1_7_0_RX2_CHFLT_COE1_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE1_7_0_RX2_CHFLT_COE1_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE2_7_0_DEFAULT 0x0C |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE2_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE2_7_0_RX2_CHFLT_COE2_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE2_7_0_RX2_CHFLT_COE2_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE2_7_0_RX2_CHFLT_COE2_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE2_7_0_RX2_CHFLT_COE2_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE3_7_0_DEFAULT 0x16 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE3_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE3_7_0_RX2_CHFLT_COE3_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE3_7_0_RX2_CHFLT_COE3_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE3_7_0_RX2_CHFLT_COE3_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE3_7_0_RX2_CHFLT_COE3_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE4_7_0_DEFAULT 0x17 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE4_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE4_7_0_RX2_CHFLT_COE4_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE4_7_0_RX2_CHFLT_COE4_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE4_7_0_RX2_CHFLT_COE4_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE4_7_0_RX2_CHFLT_COE4_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE5_7_0_DEFAULT 0x05 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE5_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE5_7_0_RX2_CHFLT_COE5_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE5_7_0_RX2_CHFLT_COE5_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE5_7_0_RX2_CHFLT_COE5_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE5_7_0_RX2_CHFLT_COE5_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE6_7_0_DEFAULT 0xDE |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE6_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE6_7_0_RX2_CHFLT_COE6_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE6_7_0_RX2_CHFLT_COE6_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE6_7_0_RX2_CHFLT_COE6_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE6_7_0_RX2_CHFLT_COE6_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_DEFAULT 0xB8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_RX2_CHFLT_COE7_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_RX2_CHFLT_COE7_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_RX2_CHFLT_COE7_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_RX2_CHFLT_COE7_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE8_7_0_DEFAULT 0xB5 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE8_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE8_7_0_RX2_CHFLT_COE8_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE8_7_0_RX2_CHFLT_COE8_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE8_7_0_RX2_CHFLT_COE8_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE8_7_0_RX2_CHFLT_COE8_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE9_7_0_DEFAULT 0xF5 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE9_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE9_7_0_RX2_CHFLT_COE9_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE9_7_0_RX2_CHFLT_COE9_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE9_7_0_RX2_CHFLT_COE9_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COE9_7_0_RX2_CHFLT_COE9_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_DEFAULT 0x15 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE10_9_8_LSB 6 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE10_9_8_MASK 0xC0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE10_9_8_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE10_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE11_9_8_LSB 4 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE11_9_8_MASK 0x30 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE11_9_8_MSB 5 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE11_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE12_9_8_LSB 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE12_9_8_MASK 0xC |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE12_9_8_MSB 3 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE12_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE13_9_8_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE13_9_8_MASK 0x3 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE13_9_8_MSB 1 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM0_RX2COE13_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_DEFAULT 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE6_9_8_LSB 6 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE6_9_8_MASK 0xC0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE6_9_8_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE6_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE7_9_8_LSB 4 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE7_9_8_MASK 0x30 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE7_9_8_MSB 5 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE7_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE8_9_8_LSB 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE8_9_8_MASK 0xC |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE8_9_8_MSB 3 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE8_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE9_9_8_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE9_9_8_MASK 0x3 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE9_9_8_MSB 1 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM1_RX2COE9_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_DEFAULT 0x00 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE2_9_8_LSB 6 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE2_9_8_MASK 0xC0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE2_9_8_MSB 7 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE2_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE3_9_8_LSB 4 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE3_9_8_MASK 0x30 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE3_9_8_MSB 5 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE3_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE4_9_8_LSB 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE4_9_8_MASK 0xC |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE4_9_8_MSB 3 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE4_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE5_9_8_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE5_9_8_MASK 0x3 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE5_9_8_MSB 1 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM2_RX2COE5_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM3_DEFAULT 0x00 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM3_MASK 0xFF |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM3_RX2COE0_9_8_LSB 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM3_RX2COE0_9_8_MASK 0xC |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM3_RX2COE0_9_8_MSB 3 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM3_RX2COE0_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM3_RX2COE1_9_8_LSB 0 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM3_RX2COE1_9_8_MASK 0x3 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM3_RX2COE1_9_8_MSB 1 |
| #define SI446X_PROP_MODEM_CHFLT_RX2_CHFLT_COEM3_RX2COE1_9_8_SIZE 2 |
| #define SI446X_PROP_MODEM_DATA_RATE_0_DEFAULT 0x40 |
| #define SI446X_PROP_MODEM_DATA_RATE_0_DR_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_DATA_RATE_0_DR_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_DATA_RATE_0_DR_7_0_MAX 255 |
| #define SI446X_PROP_MODEM_DATA_RATE_0_DR_7_0_MIN 0 |
| #define SI446X_PROP_MODEM_DATA_RATE_0_DR_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_DATA_RATE_0_DR_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_DATA_RATE_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_DATA_RATE_1_DEFAULT 0x42 |
| #define SI446X_PROP_MODEM_DATA_RATE_1_DR_15_8_LSB 0 |
| #define SI446X_PROP_MODEM_DATA_RATE_1_DR_15_8_MASK 0xFF |
| #define SI446X_PROP_MODEM_DATA_RATE_1_DR_15_8_MAX 255 |
| #define SI446X_PROP_MODEM_DATA_RATE_1_DR_15_8_MIN 0 |
| #define SI446X_PROP_MODEM_DATA_RATE_1_DR_15_8_MSB 7 |
| #define SI446X_PROP_MODEM_DATA_RATE_1_DR_15_8_SIZE 8 |
| #define SI446X_PROP_MODEM_DATA_RATE_1_MASK 0xFF |
| #define SI446X_PROP_MODEM_DATA_RATE_2_DEFAULT 0x0F |
| #define SI446X_PROP_MODEM_DATA_RATE_2_DR_23_16_LSB 0 |
| #define SI446X_PROP_MODEM_DATA_RATE_2_DR_23_16_MASK 0xFF |
| #define SI446X_PROP_MODEM_DATA_RATE_2_DR_23_16_MAX 255 |
| #define SI446X_PROP_MODEM_DATA_RATE_2_DR_23_16_MIN 0 |
| #define SI446X_PROP_MODEM_DATA_RATE_2_DR_23_16_MSB 7 |
| #define SI446X_PROP_MODEM_DATA_RATE_2_DR_23_16_SIZE 8 |
| #define SI446X_PROP_MODEM_DATA_RATE_2_MASK 0xFF |
| #define SI446X_PROP_MODEM_FREQ_DEV_0_DEFAULT 0xD3 |
| #define SI446X_PROP_MODEM_FREQ_DEV_0_FREQDEV_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_FREQ_DEV_0_FREQDEV_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_FREQ_DEV_0_FREQDEV_7_0_MAX 255 |
| #define SI446X_PROP_MODEM_FREQ_DEV_0_FREQDEV_7_0_MIN 0 |
| #define SI446X_PROP_MODEM_FREQ_DEV_0_FREQDEV_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_FREQ_DEV_0_FREQDEV_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_FREQ_DEV_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_FREQ_DEV_1_DEFAULT 0x06 |
| #define SI446X_PROP_MODEM_FREQ_DEV_1_FREQDEV_15_8_LSB 0 |
| #define SI446X_PROP_MODEM_FREQ_DEV_1_FREQDEV_15_8_MASK 0xFF |
| #define SI446X_PROP_MODEM_FREQ_DEV_1_FREQDEV_15_8_MAX 255 |
| #define SI446X_PROP_MODEM_FREQ_DEV_1_FREQDEV_15_8_MIN 0 |
| #define SI446X_PROP_MODEM_FREQ_DEV_1_FREQDEV_15_8_MSB 7 |
| #define SI446X_PROP_MODEM_FREQ_DEV_1_FREQDEV_15_8_SIZE 8 |
| #define SI446X_PROP_MODEM_FREQ_DEV_1_MASK 0xFF |
| #define SI446X_PROP_MODEM_FREQ_DEV_2_DEFAULT 0x00 |
| #define SI446X_PROP_MODEM_FREQ_DEV_2_FREQDEV_16_BIT 0x1 |
| #define SI446X_PROP_MODEM_FREQ_DEV_2_FREQDEV_16_LSB 0 |
| #define SI446X_PROP_MODEM_FREQ_DEV_2_FREQDEV_16_MASK 0x1 |
| #define SI446X_PROP_MODEM_FREQ_DEV_2_FREQDEV_16_MSB 0 |
| #define SI446X_PROP_MODEM_FREQ_DEV_2_FREQDEV_16_SIZE 1 |
| #define SI446X_PROP_MODEM_FREQ_DEV_2_MASK 0xFF |
| #define SI446X_PROP_MODEM_FREQ_OFFSET_0_DEFAULT 0x00 |
| #define SI446X_PROP_MODEM_FREQ_OFFSET_0_FREQOFFSET_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_FREQ_OFFSET_0_FREQOFFSET_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_FREQ_OFFSET_0_FREQOFFSET_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_FREQ_OFFSET_0_FREQOFFSET_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_FREQ_OFFSET_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_FREQ_OFFSET_1_DEFAULT 0x00 |
| #define SI446X_PROP_MODEM_FREQ_OFFSET_1_FREQOFFSET_15_8_LSB 0 |
| #define SI446X_PROP_MODEM_FREQ_OFFSET_1_FREQOFFSET_15_8_MASK 0xFF |
| #define SI446X_PROP_MODEM_FREQ_OFFSET_1_FREQOFFSET_15_8_MSB 7 |
| #define SI446X_PROP_MODEM_FREQ_OFFSET_1_FREQOFFSET_15_8_SIZE 8 |
| #define SI446X_PROP_MODEM_FREQ_OFFSET_1_MASK 0xFF |
| #define SI446X_PROP_MODEM_MAP_CONTROL_DEFAULT 0x80 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_FD_BIT 0x10 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_FD_LSB 4 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_FD_MASK 0x10 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_FD_MSB 4 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_FD_SIZE 1 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_RXBIT_BIT 0x40 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_RXBIT_LSB 6 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_RXBIT_MASK 0x40 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_RXBIT_MSB 6 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_RXBIT_SIZE 1 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_TXBIT_BIT 0x20 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_TXBIT_LSB 5 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_TXBIT_MASK 0x20 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_TXBIT_MSB 5 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENINV_TXBIT_SIZE 1 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENMANCH_BIT 0x80 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENMANCH_LSB 7 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENMANCH_MASK 0x80 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENMANCH_MSB 7 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_ENMANCH_SIZE 1 |
| #define SI446X_PROP_MODEM_MAP_CONTROL_MASK 0xFF |
| #define SI446X_PROP_MODEM_MOD_TYPE_DEFAULT 0x02 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MASK 0xFF |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_SOURCE_ENUM_DIRECT 1 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_SOURCE_ENUM_PACKET 0 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_SOURCE_ENUM_PSEUDO 2 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_SOURCE_LSB 3 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_SOURCE_MASK 0x18 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_SOURCE_MSB 4 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_SOURCE_SIZE 2 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_TYPE_ENUM_2FSK 2 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_TYPE_ENUM_2GFSK 3 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_TYPE_ENUM_4FSK 4 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_TYPE_ENUM_4GFSK 5 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_TYPE_ENUM_CW 0 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_TYPE_ENUM_OOK 1 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_TYPE_LSB 0 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_TYPE_MASK 0x7 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_TYPE_MSB 2 |
| #define SI446X_PROP_MODEM_MOD_TYPE_MOD_TYPE_SIZE 3 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_GPIO_ENUM_GPIO0 0 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_GPIO_ENUM_GPIO1 1 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_GPIO_ENUM_GPIO2 2 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_GPIO_ENUM_GPIO3 3 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_GPIO_LSB 5 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_GPIO_MASK 0x60 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_GPIO_MSB 6 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_GPIO_SIZE 2 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_TYPE_BIT 0x80 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_TYPE_ENUM_ASYNC 1 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_TYPE_ENUM_SYNC 0 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_TYPE_LSB 7 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_TYPE_MASK 0x80 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_TYPE_MSB 7 |
| #define SI446X_PROP_MODEM_MOD_TYPE_TX_DIRECT_MODE_TYPE_SIZE 1 |
| #define SI446X_PROP_MODEM_OOKZEROIF_RB_0_DEFAULT 0x00 |
| #define SI446X_PROP_MODEM_OOKZEROIF_RB_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_OOKZEROIF_RB_0_RB_7_0_LSB 0 |
| #define SI446X_PROP_MODEM_OOKZEROIF_RB_0_RB_7_0_MASK 0xFF |
| #define SI446X_PROP_MODEM_OOKZEROIF_RB_0_RB_7_0_MSB 7 |
| #define SI446X_PROP_MODEM_OOKZEROIF_RB_0_RB_7_0_SIZE 8 |
| #define SI446X_PROP_MODEM_RSSI_COMP_DEFAULT 0x32 |
| #define SI446X_PROP_MODEM_RSSI_COMP_MASK 0xFF |
| #define SI446X_PROP_MODEM_RSSI_COMP_RSSI_COMP_LSB 0 |
| #define SI446X_PROP_MODEM_RSSI_COMP_RSSI_COMP_MASK 0x7F |
| #define SI446X_PROP_MODEM_RSSI_COMP_RSSI_COMP_MAX 127 |
| #define SI446X_PROP_MODEM_RSSI_COMP_RSSI_COMP_MIN 0 |
| #define SI446X_PROP_MODEM_RSSI_COMP_RSSI_COMP_MSB 6 |
| #define SI446X_PROP_MODEM_RSSI_COMP_RSSI_COMP_SIZE 7 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_DEFAULT 0x00 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_ENJMPRX_BIT 0x2 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_ENJMPRX_LSB 1 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_ENJMPRX_MASK 0x2 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_ENJMPRX_MSB 1 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_ENJMPRX_SIZE 1 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_ENRSSIJMP_BIT 0x8 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_ENRSSIJMP_LSB 3 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_ENRSSIJMP_MASK 0x8 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_ENRSSIJMP_MSB 3 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_ENRSSIJMP_SIZE 1 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_JMPDLYLEN_BIT 0x4 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_JMPDLYLEN_LSB 2 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_JMPDLYLEN_MASK 0x4 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_JMPDLYLEN_MSB 2 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_JMPDLYLEN_SIZE 1 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_MASK 0xFF |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_RSSIJMP_DWN_BIT 0x20 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_RSSIJMP_DWN_LSB 5 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_RSSIJMP_DWN_MASK 0x20 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_RSSIJMP_DWN_MSB 5 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_RSSIJMP_DWN_SIZE 1 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_RSSIJMP_UP_BIT 0x10 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_RSSIJMP_UP_LSB 4 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_RSSIJMP_UP_MASK 0x10 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_RSSIJMP_UP_MSB 4 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL2_RSSIJMP_UP_SIZE 1 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_AVERAGE_BIT 0x10 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_AVERAGE_ENUM_AVERAGE1 1 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_AVERAGE_ENUM_AVERAGE4 0 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_AVERAGE_LSB 4 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_AVERAGE_MASK 0x10 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_AVERAGE_MSB 4 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_AVERAGE_SIZE 1 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_CHECK_THRESH_AT_LATCH_BIT 0x20 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_CHECK_THRESH_AT_LATCH_ENUM_DISABLE 0 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_CHECK_THRESH_AT_LATCH_ENUM_ENABLE 1 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_CHECK_THRESH_AT_LATCH_LSB 5 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_CHECK_THRESH_AT_LATCH_MASK 0x20 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_CHECK_THRESH_AT_LATCH_MSB 5 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_CHECK_THRESH_AT_LATCH_SIZE 1 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_DEFAULT 0x01 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_LATCH_ENUM_DISABLED 0 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_LATCH_ENUM_PREAMBLE 1 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_LATCH_ENUM_RX_STATE1 3 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_LATCH_ENUM_RX_STATE2 4 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_LATCH_ENUM_RX_STATE3 5 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_LATCH_ENUM_RX_STATE4 6 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_LATCH_ENUM_RX_STATE5 7 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_LATCH_ENUM_SYNC 2 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_LATCH_LSB 0 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_LATCH_MASK 0x7 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_LATCH_MSB 2 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_LATCH_SIZE 3 |
| #define SI446X_PROP_MODEM_RSSI_CONTROL_MASK 0xFF |
| #define SI446X_PROP_MODEM_RSSI_JUMP_THRESH_DEFAULT 0x0C |
| #define SI446X_PROP_MODEM_RSSI_JUMP_THRESH_MASK 0xFF |
| #define SI446X_PROP_MODEM_RSSI_JUMP_THRESH_RSSIJMPTHD_LSB 0 |
| #define SI446X_PROP_MODEM_RSSI_JUMP_THRESH_RSSIJMPTHD_MASK 0x7F |
| #define SI446X_PROP_MODEM_RSSI_JUMP_THRESH_RSSIJMPTHD_MSB 6 |
| #define SI446X_PROP_MODEM_RSSI_JUMP_THRESH_RSSIJMPTHD_SIZE 7 |
| #define SI446X_PROP_MODEM_RSSI_THRESH_DEFAULT 0xFF |
| #define SI446X_PROP_MODEM_RSSI_THRESH_MASK 0xFF |
| #define SI446X_PROP_MODEM_RSSI_THRESH_RSSI_THRESH_LSB 0 |
| #define SI446X_PROP_MODEM_RSSI_THRESH_RSSI_THRESH_MASK 0xFF |
| #define SI446X_PROP_MODEM_RSSI_THRESH_RSSI_THRESH_MAX 255 |
| #define SI446X_PROP_MODEM_RSSI_THRESH_RSSI_THRESH_MIN 0 |
| #define SI446X_PROP_MODEM_RSSI_THRESH_RSSI_THRESH_MSB 7 |
| #define SI446X_PROP_MODEM_RSSI_THRESH_RSSI_THRESH_SIZE 8 |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_ENUM_DIFF_25 1 |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_ENUM_DIFF_50 0 |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_ENUM_SINGLE_25 3 |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_ENUM_SINGLE_50 2 |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_LSB 6 |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_MASK 0xC0 |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_MSB 7 |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_CLK_DUTY_SIZE 2 |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_DEFAULT 0x00 |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_MASK 0xFF |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_OB_LSB 0 |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_OB_MASK 0x3F |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_OB_MAX 63 |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_OB_MIN 0 |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_OB_MSB 5 |
| #define SI446X_PROP_PA_BIAS_CLKDUTY_OB_SIZE 6 |
| #define SI446X_PROP_PA_PWR_LVL_DDAC_LSB 0 |
| #define SI446X_PROP_PA_PWR_LVL_DDAC_MASK 0x7F |
| #define SI446X_PROP_PA_PWR_LVL_DDAC_MAX 127 |
| #define SI446X_PROP_PA_PWR_LVL_DDAC_MIN 0 |
| #define SI446X_PROP_PA_PWR_LVL_DDAC_MSB 6 |
| #define SI446X_PROP_PA_PWR_LVL_DDAC_SIZE 7 |
| #define SI446X_PROP_PA_PWR_LVL_DEFAULT 0x7F |
| #define SI446X_PROP_PA_PWR_LVL_MASK 0xFF |
| #define SI446X_PROP_PA_RAMP_DOWN_DELAY_DEFAULT 0x23 |
| #define SI446X_PROP_PA_RAMP_DOWN_DELAY_MASK 0xFF |
| #define SI446X_PROP_PA_RAMP_DOWN_DELAY_RAMP_DOWN_DELAY_LSB 0 |
| #define SI446X_PROP_PA_RAMP_DOWN_DELAY_RAMP_DOWN_DELAY_MASK 0xFF |
| #define SI446X_PROP_PA_RAMP_DOWN_DELAY_RAMP_DOWN_DELAY_MAX 40 |
| #define SI446X_PROP_PA_RAMP_DOWN_DELAY_RAMP_DOWN_DELAY_MIN 1 |
| #define SI446X_PROP_PA_RAMP_DOWN_DELAY_RAMP_DOWN_DELAY_MSB 7 |
| #define SI446X_PROP_PA_RAMP_DOWN_DELAY_RAMP_DOWN_DELAY_SIZE 8 |
| #define SI446X_PROP_PA_RAMP_EX_DEFAULT 0x00 |
| #define SI446X_PROP_PA_RAMP_EX_MASK 0xFF |
| #define SI446X_PROP_PA_RAMP_EX_TC_LSB 0 |
| #define SI446X_PROP_PA_RAMP_EX_TC_MASK 0xF |
| #define SI446X_PROP_PA_RAMP_EX_TC_MAX 15 |
| #define SI446X_PROP_PA_RAMP_EX_TC_MIN 0 |
| #define SI446X_PROP_PA_RAMP_EX_TC_MSB 3 |
| #define SI446X_PROP_PA_RAMP_EX_TC_SIZE 4 |
| #define SI446X_PROP_PA_RAMP_EX_VSET_LSB 4 |
| #define SI446X_PROP_PA_RAMP_EX_VSET_MASK 0xF0 |
| #define SI446X_PROP_PA_RAMP_EX_VSET_MAX 15 |
| #define SI446X_PROP_PA_RAMP_EX_VSET_MIN 0 |
| #define SI446X_PROP_PA_RAMP_EX_VSET_MSB 7 |
| #define SI446X_PROP_PA_RAMP_EX_VSET_SIZE 4 |
| #define SI446X_PROP_PA_TC_DEFAULT 0x5D |
| #define SI446X_PROP_PA_TC_FSK_MOD_DLY_ENUM_10_US 2 |
| #define SI446X_PROP_PA_TC_FSK_MOD_DLY_ENUM_14_US 3 |
| #define SI446X_PROP_PA_TC_FSK_MOD_DLY_ENUM_18_US 4 |
| #define SI446X_PROP_PA_TC_FSK_MOD_DLY_ENUM_22_US 5 |
| #define SI446X_PROP_PA_TC_FSK_MOD_DLY_ENUM_26_US 6 |
| #define SI446X_PROP_PA_TC_FSK_MOD_DLY_ENUM_2_US 0 |
| #define SI446X_PROP_PA_TC_FSK_MOD_DLY_ENUM_30_US 7 |
| #define SI446X_PROP_PA_TC_FSK_MOD_DLY_ENUM_6_US 1 |
| #define SI446X_PROP_PA_TC_FSK_MOD_DLY_LSB 5 |
| #define SI446X_PROP_PA_TC_FSK_MOD_DLY_MASK 0xE0 |
| #define SI446X_PROP_PA_TC_FSK_MOD_DLY_MSB 7 |
| #define SI446X_PROP_PA_TC_FSK_MOD_DLY_SIZE 3 |
| #define SI446X_PROP_PA_TC_MASK 0xFF |
| #define SI446X_PROP_PA_TC_TC_LSB 0 |
| #define SI446X_PROP_PA_TC_TC_MASK 0x1F |
| #define SI446X_PROP_PA_TC_TC_MAX 31 |
| #define SI446X_PROP_PA_TC_TC_MIN 0 |
| #define SI446X_PROP_PA_TC_TC_MSB 4 |
| #define SI446X_PROP_PA_TC_TC_SIZE 5 |
| #define SI446X_PROP_PKT_CONFIG1_4FSK_EN_BIT 0x20 |
| #define SI446X_PROP_PKT_CONFIG1_4FSK_EN_LSB 5 |
| #define SI446X_PROP_PKT_CONFIG1_4FSK_EN_MASK 0x20 |
| #define SI446X_PROP_PKT_CONFIG1_4FSK_EN_MSB 5 |
| #define SI446X_PROP_PKT_CONFIG1_4FSK_EN_SIZE 1 |
| #define SI446X_PROP_PKT_CONFIG1_BIT_ORDER_BIT 0x1 |
| #define SI446X_PROP_PKT_CONFIG1_BIT_ORDER_LSB 0 |
| #define SI446X_PROP_PKT_CONFIG1_BIT_ORDER_MASK 0x1 |
| #define SI446X_PROP_PKT_CONFIG1_BIT_ORDER_MSB 0 |
| #define SI446X_PROP_PKT_CONFIG1_BIT_ORDER_SIZE 1 |
| #define SI446X_PROP_PKT_CONFIG1_CRC_ENDIAN_BIT 0x2 |
| #define SI446X_PROP_PKT_CONFIG1_CRC_ENDIAN_LSB 1 |
| #define SI446X_PROP_PKT_CONFIG1_CRC_ENDIAN_MASK 0x2 |
| #define SI446X_PROP_PKT_CONFIG1_CRC_ENDIAN_MSB 1 |
| #define SI446X_PROP_PKT_CONFIG1_CRC_ENDIAN_SIZE 1 |
| #define SI446X_PROP_PKT_CONFIG1_CRC_INVERT_BIT 0x4 |
| #define SI446X_PROP_PKT_CONFIG1_CRC_INVERT_LSB 2 |
| #define SI446X_PROP_PKT_CONFIG1_CRC_INVERT_MASK 0x4 |
| #define SI446X_PROP_PKT_CONFIG1_CRC_INVERT_MSB 2 |
| #define SI446X_PROP_PKT_CONFIG1_CRC_INVERT_SIZE 1 |
| #define SI446X_PROP_PKT_CONFIG1_DEFAULT 0 |
| #define SI446X_PROP_PKT_CONFIG1_MANCH_POL_BIT 0x8 |
| #define SI446X_PROP_PKT_CONFIG1_MANCH_POL_LSB 3 |
| #define SI446X_PROP_PKT_CONFIG1_MANCH_POL_MASK 0x8 |
| #define SI446X_PROP_PKT_CONFIG1_MANCH_POL_MSB 3 |
| #define SI446X_PROP_PKT_CONFIG1_MANCH_POL_SIZE 1 |
| #define SI446X_PROP_PKT_CONFIG1_MASK 0xFF |
| #define SI446X_PROP_PKT_CONFIG1_PH_FIELD_SPLIT_BIT 0x80 |
| #define SI446X_PROP_PKT_CONFIG1_PH_FIELD_SPLIT_LSB 7 |
| #define SI446X_PROP_PKT_CONFIG1_PH_FIELD_SPLIT_MASK 0x80 |
| #define SI446X_PROP_PKT_CONFIG1_PH_FIELD_SPLIT_MSB 7 |
| #define SI446X_PROP_PKT_CONFIG1_PH_FIELD_SPLIT_SIZE 1 |
| #define SI446X_PROP_PKT_CONFIG1_PH_RX_DISABLE_BIT 0x40 |
| #define SI446X_PROP_PKT_CONFIG1_PH_RX_DISABLE_LSB 6 |
| #define SI446X_PROP_PKT_CONFIG1_PH_RX_DISABLE_MASK 0x40 |
| #define SI446X_PROP_PKT_CONFIG1_PH_RX_DISABLE_MSB 6 |
| #define SI446X_PROP_PKT_CONFIG1_PH_RX_DISABLE_SIZE 1 |
| #define SI446X_PROP_PKT_CONFIG1_RX_MULTI_PKT_BIT 0x10 |
| #define SI446X_PROP_PKT_CONFIG1_RX_MULTI_PKT_LSB 4 |
| #define SI446X_PROP_PKT_CONFIG1_RX_MULTI_PKT_MASK 0x10 |
| #define SI446X_PROP_PKT_CONFIG1_RX_MULTI_PKT_MSB 4 |
| #define SI446X_PROP_PKT_CONFIG1_RX_MULTI_PKT_SIZE 1 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_POLYNOMIAL_ENUM_BAICHEVA_16 3 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_POLYNOMIAL_ENUM_CASTAGNOLI 8 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_POLYNOMIAL_ENUM_CCITT_16 5 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_POLYNOMIAL_ENUM_CRC_16_IBM 4 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_POLYNOMIAL_ENUM_IEC_16 2 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_POLYNOMIAL_ENUM_IEEE_802_3 7 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_POLYNOMIAL_ENUM_ITU_T_CRC8 1 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_POLYNOMIAL_ENUM_KOOPMAN 6 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_POLYNOMIAL_ENUM_NO_CRC 0 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_POLYNOMIAL_LSB 0 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_POLYNOMIAL_MASK 0xF |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_POLYNOMIAL_MSB 3 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_POLYNOMIAL_SIZE 4 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_SEED_BIT 0x80 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_SEED_LSB 7 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_SEED_MASK 0x80 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_SEED_MSB 7 |
| #define SI446X_PROP_PKT_CRC_CONFIG_CRC_SEED_SIZE 1 |
| #define SI446X_PROP_PKT_CRC_CONFIG_DEFAULT 0 |
| #define SI446X_PROP_PKT_CRC_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_4FSK_BIT 0x10 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_4FSK_LSB 4 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_4FSK_MASK 0x10 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_4FSK_MSB 4 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_4FSK_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_MANCH_BIT 0x1 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_MANCH_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_MANCH_MASK 0x1 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_MANCH_MSB 0 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_MANCH_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_PN_START_BIT 0x4 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_PN_START_LSB 2 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_PN_START_MASK 0x4 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_PN_START_MSB 2 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_PN_START_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_WHITEN_BIT 0x2 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_WHITEN_LSB 1 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_WHITEN_MASK 0x2 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_WHITEN_MSB 1 |
| #define SI446X_PROP_PKT_FIELD_1_CONFIG_WHITEN_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CHECK_CRC_BIT 0x8 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CHECK_CRC_LSB 3 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CHECK_CRC_MASK 0x8 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CHECK_CRC_MSB 3 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CHECK_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CRC_ENABLE_BIT 0x2 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CRC_ENABLE_LSB 1 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CRC_ENABLE_MASK 0x2 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CRC_ENABLE_MSB 1 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CRC_ENABLE_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CRC_START_BIT 0x80 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CRC_START_LSB 7 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CRC_START_MASK 0x80 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CRC_START_MSB 7 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_CRC_START_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_SEND_CRC_BIT 0x20 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_SEND_CRC_LSB 5 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_SEND_CRC_MASK 0x20 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_SEND_CRC_MSB 5 |
| #define SI446X_PROP_PKT_FIELD_1_CRC_CONFIG_SEND_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_1_LENGTH_12_8_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_1_LENGTH_12_8_FIELD_1_LENGTH_12_8_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_1_LENGTH_12_8_FIELD_1_LENGTH_12_8_MASK 0x1F |
| #define SI446X_PROP_PKT_FIELD_1_LENGTH_12_8_FIELD_1_LENGTH_12_8_MSB 4 |
| #define SI446X_PROP_PKT_FIELD_1_LENGTH_12_8_FIELD_1_LENGTH_12_8_SIZE 5 |
| #define SI446X_PROP_PKT_FIELD_1_LENGTH_12_8_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_1_LENGTH_7_0_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_1_LENGTH_7_0_FIELD_1_LENGTH_7_0_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_1_LENGTH_7_0_FIELD_1_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_1_LENGTH_7_0_FIELD_1_LENGTH_7_0_MAX 0xff |
| #define SI446X_PROP_PKT_FIELD_1_LENGTH_7_0_FIELD_1_LENGTH_7_0_MIN 0 |
| #define SI446X_PROP_PKT_FIELD_1_LENGTH_7_0_FIELD_1_LENGTH_7_0_MSB 7 |
| #define SI446X_PROP_PKT_FIELD_1_LENGTH_7_0_FIELD_1_LENGTH_7_0_SIZE 8 |
| #define SI446X_PROP_PKT_FIELD_1_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_4FSK_BIT 0x10 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_4FSK_LSB 4 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_4FSK_MASK 0x10 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_4FSK_MSB 4 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_4FSK_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_MANCH_BIT 0x1 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_MANCH_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_MANCH_MASK 0x1 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_MANCH_MSB 0 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_MANCH_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_RESERVED_BIT 0x4 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_RESERVED_LSB 2 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_RESERVED_MASK 0x4 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_RESERVED_MSB 2 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_RESERVED_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_WHITEN_BIT 0x2 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_WHITEN_LSB 1 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_WHITEN_MASK 0x2 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_WHITEN_MSB 1 |
| #define SI446X_PROP_PKT_FIELD_2_CONFIG_WHITEN_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_CHECK_CRC_BIT 0x8 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_CHECK_CRC_LSB 3 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_CHECK_CRC_MASK 0x8 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_CHECK_CRC_MSB 3 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_CHECK_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_CRC_ENABLE_BIT 0x2 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_CRC_ENABLE_LSB 1 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_CRC_ENABLE_MASK 0x2 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_CRC_ENABLE_MSB 1 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_CRC_ENABLE_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_RESERVED_LSB 6 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_RESERVED_MASK 0xC0 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_RESERVED_MSB 7 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_RESERVED_SIZE 2 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_SEND_CRC_BIT 0x20 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_SEND_CRC_LSB 5 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_SEND_CRC_MASK 0x20 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_SEND_CRC_MSB 5 |
| #define SI446X_PROP_PKT_FIELD_2_CRC_CONFIG_SEND_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_2_LENGTH_12_8_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_2_LENGTH_12_8_FIELD_2_LENGTH_12_8_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_2_LENGTH_12_8_FIELD_2_LENGTH_12_8_MASK 0x1F |
| #define SI446X_PROP_PKT_FIELD_2_LENGTH_12_8_FIELD_2_LENGTH_12_8_MSB 4 |
| #define SI446X_PROP_PKT_FIELD_2_LENGTH_12_8_FIELD_2_LENGTH_12_8_SIZE 5 |
| #define SI446X_PROP_PKT_FIELD_2_LENGTH_12_8_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_2_LENGTH_7_0_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_2_LENGTH_7_0_FIELD_2_LENGTH_7_0_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_2_LENGTH_7_0_FIELD_2_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_2_LENGTH_7_0_FIELD_2_LENGTH_7_0_MAX 0xff |
| #define SI446X_PROP_PKT_FIELD_2_LENGTH_7_0_FIELD_2_LENGTH_7_0_MIN 0 |
| #define SI446X_PROP_PKT_FIELD_2_LENGTH_7_0_FIELD_2_LENGTH_7_0_MSB 7 |
| #define SI446X_PROP_PKT_FIELD_2_LENGTH_7_0_FIELD_2_LENGTH_7_0_SIZE 8 |
| #define SI446X_PROP_PKT_FIELD_2_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_4FSK_BIT 0x10 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_4FSK_LSB 4 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_4FSK_MASK 0x10 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_4FSK_MSB 4 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_4FSK_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_MANCH_BIT 0x1 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_MANCH_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_MANCH_MASK 0x1 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_MANCH_MSB 0 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_MANCH_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_RESERVED_BIT 0x4 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_RESERVED_LSB 2 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_RESERVED_MASK 0x4 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_RESERVED_MSB 2 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_RESERVED_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_WHITEN_BIT 0x2 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_WHITEN_LSB 1 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_WHITEN_MASK 0x2 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_WHITEN_MSB 1 |
| #define SI446X_PROP_PKT_FIELD_3_CONFIG_WHITEN_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_CHECK_CRC_BIT 0x8 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_CHECK_CRC_LSB 3 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_CHECK_CRC_MASK 0x8 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_CHECK_CRC_MSB 3 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_CHECK_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_CRC_ENABLE_BIT 0x2 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_CRC_ENABLE_LSB 1 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_CRC_ENABLE_MASK 0x2 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_CRC_ENABLE_MSB 1 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_CRC_ENABLE_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_RESERVED_LSB 6 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_RESERVED_MASK 0xC0 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_RESERVED_MSB 7 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_RESERVED_SIZE 2 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_SEND_CRC_BIT 0x20 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_SEND_CRC_LSB 5 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_SEND_CRC_MASK 0x20 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_SEND_CRC_MSB 5 |
| #define SI446X_PROP_PKT_FIELD_3_CRC_CONFIG_SEND_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_3_LENGTH_12_8_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_3_LENGTH_12_8_FIELD_3_LENGTH_12_8_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_3_LENGTH_12_8_FIELD_3_LENGTH_12_8_MASK 0x1F |
| #define SI446X_PROP_PKT_FIELD_3_LENGTH_12_8_FIELD_3_LENGTH_12_8_MSB 4 |
| #define SI446X_PROP_PKT_FIELD_3_LENGTH_12_8_FIELD_3_LENGTH_12_8_SIZE 5 |
| #define SI446X_PROP_PKT_FIELD_3_LENGTH_12_8_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_3_LENGTH_7_0_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_3_LENGTH_7_0_FIELD_3_LENGTH_7_0_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_3_LENGTH_7_0_FIELD_3_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_3_LENGTH_7_0_FIELD_3_LENGTH_7_0_MAX 0xff |
| #define SI446X_PROP_PKT_FIELD_3_LENGTH_7_0_FIELD_3_LENGTH_7_0_MIN 0 |
| #define SI446X_PROP_PKT_FIELD_3_LENGTH_7_0_FIELD_3_LENGTH_7_0_MSB 7 |
| #define SI446X_PROP_PKT_FIELD_3_LENGTH_7_0_FIELD_3_LENGTH_7_0_SIZE 8 |
| #define SI446X_PROP_PKT_FIELD_3_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_4FSK_BIT 0x10 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_4FSK_LSB 4 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_4FSK_MASK 0x10 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_4FSK_MSB 4 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_4FSK_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_MANCH_BIT 0x1 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_MANCH_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_MANCH_MASK 0x1 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_MANCH_MSB 0 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_MANCH_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_RESERVED_BIT 0x4 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_RESERVED_LSB 2 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_RESERVED_MASK 0x4 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_RESERVED_MSB 2 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_RESERVED_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_WHITEN_BIT 0x2 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_WHITEN_LSB 1 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_WHITEN_MASK 0x2 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_WHITEN_MSB 1 |
| #define SI446X_PROP_PKT_FIELD_4_CONFIG_WHITEN_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_CHECK_CRC_BIT 0x8 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_CHECK_CRC_LSB 3 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_CHECK_CRC_MASK 0x8 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_CHECK_CRC_MSB 3 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_CHECK_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_CRC_ENABLE_BIT 0x2 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_CRC_ENABLE_LSB 1 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_CRC_ENABLE_MASK 0x2 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_CRC_ENABLE_MSB 1 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_CRC_ENABLE_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_RESERVED_LSB 6 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_RESERVED_MASK 0xC0 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_RESERVED_MSB 7 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_RESERVED_SIZE 2 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_SEND_CRC_BIT 0x20 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_SEND_CRC_LSB 5 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_SEND_CRC_MASK 0x20 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_SEND_CRC_MSB 5 |
| #define SI446X_PROP_PKT_FIELD_4_CRC_CONFIG_SEND_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_4_LENGTH_12_8_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_4_LENGTH_12_8_FIELD_4_LENGTH_12_8_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_4_LENGTH_12_8_FIELD_4_LENGTH_12_8_MASK 0x1F |
| #define SI446X_PROP_PKT_FIELD_4_LENGTH_12_8_FIELD_4_LENGTH_12_8_MSB 4 |
| #define SI446X_PROP_PKT_FIELD_4_LENGTH_12_8_FIELD_4_LENGTH_12_8_SIZE 5 |
| #define SI446X_PROP_PKT_FIELD_4_LENGTH_12_8_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_4_LENGTH_7_0_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_4_LENGTH_7_0_FIELD_4_LENGTH_7_0_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_4_LENGTH_7_0_FIELD_4_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_4_LENGTH_7_0_FIELD_4_LENGTH_7_0_MAX 0xff |
| #define SI446X_PROP_PKT_FIELD_4_LENGTH_7_0_FIELD_4_LENGTH_7_0_MIN 0 |
| #define SI446X_PROP_PKT_FIELD_4_LENGTH_7_0_FIELD_4_LENGTH_7_0_MSB 7 |
| #define SI446X_PROP_PKT_FIELD_4_LENGTH_7_0_FIELD_4_LENGTH_7_0_SIZE 8 |
| #define SI446X_PROP_PKT_FIELD_4_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_4FSK_BIT 0x10 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_4FSK_LSB 4 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_4FSK_MASK 0x10 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_4FSK_MSB 4 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_4FSK_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_MANCH_BIT 0x1 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_MANCH_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_MANCH_MASK 0x1 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_MANCH_MSB 0 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_MANCH_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_RESERVED_BIT 0x4 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_RESERVED_LSB 2 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_RESERVED_MASK 0x4 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_RESERVED_MSB 2 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_RESERVED_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_WHITEN_BIT 0x2 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_WHITEN_LSB 1 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_WHITEN_MASK 0x2 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_WHITEN_MSB 1 |
| #define SI446X_PROP_PKT_FIELD_5_CONFIG_WHITEN_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_CHECK_CRC_BIT 0x8 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_CHECK_CRC_LSB 3 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_CHECK_CRC_MASK 0x8 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_CHECK_CRC_MSB 3 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_CHECK_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_CRC_ENABLE_BIT 0x2 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_CRC_ENABLE_LSB 1 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_CRC_ENABLE_MASK 0x2 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_CRC_ENABLE_MSB 1 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_CRC_ENABLE_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_RESERVED_LSB 6 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_RESERVED_MASK 0xC0 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_RESERVED_MSB 7 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_RESERVED_SIZE 2 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_SEND_CRC_BIT 0x20 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_SEND_CRC_LSB 5 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_SEND_CRC_MASK 0x20 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_SEND_CRC_MSB 5 |
| #define SI446X_PROP_PKT_FIELD_5_CRC_CONFIG_SEND_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_FIELD_5_LENGTH_12_8_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_5_LENGTH_12_8_FIELD_5_LENGTH_12_8_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_5_LENGTH_12_8_FIELD_5_LENGTH_12_8_MASK 0x1F |
| #define SI446X_PROP_PKT_FIELD_5_LENGTH_12_8_FIELD_5_LENGTH_12_8_MSB 4 |
| #define SI446X_PROP_PKT_FIELD_5_LENGTH_12_8_FIELD_5_LENGTH_12_8_SIZE 5 |
| #define SI446X_PROP_PKT_FIELD_5_LENGTH_12_8_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_5_LENGTH_7_0_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_FIELD_5_LENGTH_7_0_FIELD_5_LENGTH_7_0_LSB 0 |
| #define SI446X_PROP_PKT_FIELD_5_LENGTH_7_0_FIELD_5_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_FIELD_5_LENGTH_7_0_FIELD_5_LENGTH_7_0_MAX 0xff |
| #define SI446X_PROP_PKT_FIELD_5_LENGTH_7_0_FIELD_5_LENGTH_7_0_MIN 0 |
| #define SI446X_PROP_PKT_FIELD_5_LENGTH_7_0_FIELD_5_LENGTH_7_0_MSB 7 |
| #define SI446X_PROP_PKT_FIELD_5_LENGTH_7_0_FIELD_5_LENGTH_7_0_SIZE 8 |
| #define SI446X_PROP_PKT_FIELD_5_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_LEN_ADJUST_DEFAULT 0 |
| #define SI446X_PROP_PKT_LEN_ADJUST_LEN_ADJUST_LSB 0 |
| #define SI446X_PROP_PKT_LEN_ADJUST_LEN_ADJUST_MASK 0xFF |
| #define SI446X_PROP_PKT_LEN_ADJUST_LEN_ADJUST_MAX 127 |
| #define SI446X_PROP_PKT_LEN_ADJUST_LEN_ADJUST_MIN -128 |
| #define SI446X_PROP_PKT_LEN_ADJUST_LEN_ADJUST_MSB 7 |
| #define SI446X_PROP_PKT_LEN_ADJUST_LEN_ADJUST_SIZE 8 |
| #define SI446X_PROP_PKT_LEN_ADJUST_MASK 0xFF |
| #define SI446X_PROP_PKT_LEN_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_LEN_DST_FIELD_LSB 0 |
| #define SI446X_PROP_PKT_LEN_DST_FIELD_MASK 0x7 |
| #define SI446X_PROP_PKT_LEN_DST_FIELD_MSB 2 |
| #define SI446X_PROP_PKT_LEN_DST_FIELD_SIZE 3 |
| #define SI446X_PROP_PKT_LEN_ENDIAN_BIT 0x20 |
| #define SI446X_PROP_PKT_LEN_ENDIAN_ENUM_BIG 0x1 |
| #define SI446X_PROP_PKT_LEN_ENDIAN_ENUM_LITTLE 0x0 |
| #define SI446X_PROP_PKT_LEN_ENDIAN_LSB 5 |
| #define SI446X_PROP_PKT_LEN_ENDIAN_MASK 0x20 |
| #define SI446X_PROP_PKT_LEN_ENDIAN_MSB 5 |
| #define SI446X_PROP_PKT_LEN_ENDIAN_SIZE 1 |
| #define SI446X_PROP_PKT_LEN_FIELD_SOURCE_DEFAULT 0 |
| #define SI446X_PROP_PKT_LEN_FIELD_SOURCE_MASK 0xFF |
| #define SI446X_PROP_PKT_LEN_FIELD_SOURCE_SRC_FIELD_LSB 0 |
| #define SI446X_PROP_PKT_LEN_FIELD_SOURCE_SRC_FIELD_MASK 0x7 |
| #define SI446X_PROP_PKT_LEN_FIELD_SOURCE_SRC_FIELD_MSB 2 |
| #define SI446X_PROP_PKT_LEN_FIELD_SOURCE_SRC_FIELD_SIZE 3 |
| #define SI446X_PROP_PKT_LEN_IN_FIFO_BIT 0x8 |
| #define SI446X_PROP_PKT_LEN_IN_FIFO_ENUM_CUT_OUT 0x0 |
| #define SI446X_PROP_PKT_LEN_IN_FIFO_ENUM_LEAVE_IN 0x1 |
| #define SI446X_PROP_PKT_LEN_IN_FIFO_LSB 3 |
| #define SI446X_PROP_PKT_LEN_IN_FIFO_MASK 0x8 |
| #define SI446X_PROP_PKT_LEN_IN_FIFO_MSB 3 |
| #define SI446X_PROP_PKT_LEN_IN_FIFO_SIZE 1 |
| #define SI446X_PROP_PKT_LEN_MASK 0xFF |
| #define SI446X_PROP_PKT_LEN_SIZE_BIT 0x10 |
| #define SI446X_PROP_PKT_LEN_SIZE_LSB 4 |
| #define SI446X_PROP_PKT_LEN_SIZE_MASK 0x10 |
| #define SI446X_PROP_PKT_LEN_SIZE_MSB 4 |
| #define SI446X_PROP_PKT_LEN_SIZE_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_4FSK_BIT 0x10 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_4FSK_LSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_4FSK_MASK 0x10 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_4FSK_MSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_4FSK_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_MANCH_BIT 0x1 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_MANCH_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_MANCH_MASK 0x1 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_MANCH_MSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_MANCH_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_PN_START_BIT 0x4 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_PN_START_LSB 2 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_PN_START_MASK 0x4 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_PN_START_MSB 2 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_PN_START_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_WHITEN_BIT 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_WHITEN_LSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_WHITEN_MASK 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_WHITEN_MSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CONFIG_WHITEN_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CHECK_CRC_BIT 0x8 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CHECK_CRC_LSB 3 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CHECK_CRC_MASK 0x8 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CHECK_CRC_MSB 3 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CHECK_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CRC_ENABLE_BIT 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CRC_ENABLE_LSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CRC_ENABLE_MASK 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CRC_ENABLE_MSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CRC_ENABLE_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CRC_START_BIT 0x80 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CRC_START_LSB 7 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CRC_START_MASK 0x80 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CRC_START_MSB 7 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_CRC_START_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_1_CRC_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_1_LENGTH_12_8_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_1_LENGTH_12_8_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_1_LENGTH_12_8_RX_FIELD_1_LENGTH_12_8_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_1_LENGTH_12_8_RX_FIELD_1_LENGTH_12_8_MASK 0x1F |
| #define SI446X_PROP_PKT_RX_FIELD_1_LENGTH_12_8_RX_FIELD_1_LENGTH_12_8_MSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_1_LENGTH_12_8_RX_FIELD_1_LENGTH_12_8_SIZE 5 |
| #define SI446X_PROP_PKT_RX_FIELD_1_LENGTH_7_0_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_1_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_1_LENGTH_7_0_RX_FIELD_1_LENGTH_7_0_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_1_LENGTH_7_0_RX_FIELD_1_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_1_LENGTH_7_0_RX_FIELD_1_LENGTH_7_0_MAX 0xff |
| #define SI446X_PROP_PKT_RX_FIELD_1_LENGTH_7_0_RX_FIELD_1_LENGTH_7_0_MIN 0 |
| #define SI446X_PROP_PKT_RX_FIELD_1_LENGTH_7_0_RX_FIELD_1_LENGTH_7_0_MSB 7 |
| #define SI446X_PROP_PKT_RX_FIELD_1_LENGTH_7_0_RX_FIELD_1_LENGTH_7_0_SIZE 8 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_4FSK_BIT 0x10 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_4FSK_LSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_4FSK_MASK 0x10 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_4FSK_MSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_4FSK_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_MANCH_BIT 0x1 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_MANCH_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_MANCH_MASK 0x1 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_MANCH_MSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_MANCH_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_RESERVED_BIT 0x4 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_RESERVED_LSB 2 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_RESERVED_MASK 0x4 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_RESERVED_MSB 2 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_RESERVED_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_WHITEN_BIT 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_WHITEN_LSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_WHITEN_MASK 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_WHITEN_MSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CONFIG_WHITEN_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_CHECK_CRC_BIT 0x8 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_CHECK_CRC_LSB 3 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_CHECK_CRC_MASK 0x8 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_CHECK_CRC_MSB 3 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_CHECK_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_CRC_ENABLE_BIT 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_CRC_ENABLE_LSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_CRC_ENABLE_MASK 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_CRC_ENABLE_MSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_CRC_ENABLE_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_RESERVED_LSB 6 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_RESERVED_MASK 0xC0 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_RESERVED_MSB 7 |
| #define SI446X_PROP_PKT_RX_FIELD_2_CRC_CONFIG_RESERVED_SIZE 2 |
| #define SI446X_PROP_PKT_RX_FIELD_2_LENGTH_12_8_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_2_LENGTH_12_8_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_2_LENGTH_12_8_RX_FIELD_2_LENGTH_12_8_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_2_LENGTH_12_8_RX_FIELD_2_LENGTH_12_8_MASK 0x1F |
| #define SI446X_PROP_PKT_RX_FIELD_2_LENGTH_12_8_RX_FIELD_2_LENGTH_12_8_MSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_2_LENGTH_12_8_RX_FIELD_2_LENGTH_12_8_SIZE 5 |
| #define SI446X_PROP_PKT_RX_FIELD_2_LENGTH_7_0_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_2_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_2_LENGTH_7_0_RX_FIELD_2_LENGTH_7_0_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_2_LENGTH_7_0_RX_FIELD_2_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_2_LENGTH_7_0_RX_FIELD_2_LENGTH_7_0_MAX 0xff |
| #define SI446X_PROP_PKT_RX_FIELD_2_LENGTH_7_0_RX_FIELD_2_LENGTH_7_0_MIN 0 |
| #define SI446X_PROP_PKT_RX_FIELD_2_LENGTH_7_0_RX_FIELD_2_LENGTH_7_0_MSB 7 |
| #define SI446X_PROP_PKT_RX_FIELD_2_LENGTH_7_0_RX_FIELD_2_LENGTH_7_0_SIZE 8 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_4FSK_BIT 0x10 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_4FSK_LSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_4FSK_MASK 0x10 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_4FSK_MSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_4FSK_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_MANCH_BIT 0x1 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_MANCH_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_MANCH_MASK 0x1 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_MANCH_MSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_MANCH_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_RESERVED_BIT 0x4 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_RESERVED_LSB 2 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_RESERVED_MASK 0x4 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_RESERVED_MSB 2 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_RESERVED_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_WHITEN_BIT 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_WHITEN_LSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_WHITEN_MASK 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_WHITEN_MSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CONFIG_WHITEN_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_CHECK_CRC_BIT 0x8 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_CHECK_CRC_LSB 3 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_CHECK_CRC_MASK 0x8 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_CHECK_CRC_MSB 3 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_CHECK_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_CRC_ENABLE_BIT 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_CRC_ENABLE_LSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_CRC_ENABLE_MASK 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_CRC_ENABLE_MSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_CRC_ENABLE_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_RESERVED_LSB 6 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_RESERVED_MASK 0xC0 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_RESERVED_MSB 7 |
| #define SI446X_PROP_PKT_RX_FIELD_3_CRC_CONFIG_RESERVED_SIZE 2 |
| #define SI446X_PROP_PKT_RX_FIELD_3_LENGTH_12_8_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_3_LENGTH_12_8_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_3_LENGTH_12_8_RX_FIELD_3_LENGTH_12_8_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_3_LENGTH_12_8_RX_FIELD_3_LENGTH_12_8_MASK 0x1F |
| #define SI446X_PROP_PKT_RX_FIELD_3_LENGTH_12_8_RX_FIELD_3_LENGTH_12_8_MSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_3_LENGTH_12_8_RX_FIELD_3_LENGTH_12_8_SIZE 5 |
| #define SI446X_PROP_PKT_RX_FIELD_3_LENGTH_7_0_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_3_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_3_LENGTH_7_0_RX_FIELD_3_LENGTH_7_0_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_3_LENGTH_7_0_RX_FIELD_3_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_3_LENGTH_7_0_RX_FIELD_3_LENGTH_7_0_MAX 0xff |
| #define SI446X_PROP_PKT_RX_FIELD_3_LENGTH_7_0_RX_FIELD_3_LENGTH_7_0_MIN 0 |
| #define SI446X_PROP_PKT_RX_FIELD_3_LENGTH_7_0_RX_FIELD_3_LENGTH_7_0_MSB 7 |
| #define SI446X_PROP_PKT_RX_FIELD_3_LENGTH_7_0_RX_FIELD_3_LENGTH_7_0_SIZE 8 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_4FSK_BIT 0x10 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_4FSK_LSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_4FSK_MASK 0x10 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_4FSK_MSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_4FSK_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_MANCH_BIT 0x1 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_MANCH_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_MANCH_MASK 0x1 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_MANCH_MSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_MANCH_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_RESERVED_BIT 0x4 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_RESERVED_LSB 2 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_RESERVED_MASK 0x4 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_RESERVED_MSB 2 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_RESERVED_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_WHITEN_BIT 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_WHITEN_LSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_WHITEN_MASK 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_WHITEN_MSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CONFIG_WHITEN_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_CHECK_CRC_BIT 0x8 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_CHECK_CRC_LSB 3 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_CHECK_CRC_MASK 0x8 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_CHECK_CRC_MSB 3 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_CHECK_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_CRC_ENABLE_BIT 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_CRC_ENABLE_LSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_CRC_ENABLE_MASK 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_CRC_ENABLE_MSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_CRC_ENABLE_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_RESERVED_LSB 6 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_RESERVED_MASK 0xC0 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_RESERVED_MSB 7 |
| #define SI446X_PROP_PKT_RX_FIELD_4_CRC_CONFIG_RESERVED_SIZE 2 |
| #define SI446X_PROP_PKT_RX_FIELD_4_LENGTH_12_8_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_4_LENGTH_12_8_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_4_LENGTH_12_8_RX_FIELD_4_LENGTH_12_8_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_4_LENGTH_12_8_RX_FIELD_4_LENGTH_12_8_MASK 0x1F |
| #define SI446X_PROP_PKT_RX_FIELD_4_LENGTH_12_8_RX_FIELD_4_LENGTH_12_8_MSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_4_LENGTH_12_8_RX_FIELD_4_LENGTH_12_8_SIZE 5 |
| #define SI446X_PROP_PKT_RX_FIELD_4_LENGTH_7_0_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_4_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_4_LENGTH_7_0_RX_FIELD_4_LENGTH_7_0_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_4_LENGTH_7_0_RX_FIELD_4_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_4_LENGTH_7_0_RX_FIELD_4_LENGTH_7_0_MAX 0xff |
| #define SI446X_PROP_PKT_RX_FIELD_4_LENGTH_7_0_RX_FIELD_4_LENGTH_7_0_MIN 0 |
| #define SI446X_PROP_PKT_RX_FIELD_4_LENGTH_7_0_RX_FIELD_4_LENGTH_7_0_MSB 7 |
| #define SI446X_PROP_PKT_RX_FIELD_4_LENGTH_7_0_RX_FIELD_4_LENGTH_7_0_SIZE 8 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_4FSK_BIT 0x10 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_4FSK_LSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_4FSK_MASK 0x10 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_4FSK_MSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_4FSK_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_MANCH_BIT 0x1 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_MANCH_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_MANCH_MASK 0x1 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_MANCH_MSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_MANCH_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_RESERVED_BIT 0x4 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_RESERVED_LSB 2 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_RESERVED_MASK 0x4 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_RESERVED_MSB 2 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_RESERVED_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_WHITEN_BIT 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_WHITEN_LSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_WHITEN_MASK 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_WHITEN_MSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CONFIG_WHITEN_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_CHECK_CRC_BIT 0x8 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_CHECK_CRC_LSB 3 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_CHECK_CRC_MASK 0x8 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_CHECK_CRC_MSB 3 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_CHECK_CRC_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_CRC_ENABLE_BIT 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_CRC_ENABLE_LSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_CRC_ENABLE_MASK 0x2 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_CRC_ENABLE_MSB 1 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_CRC_ENABLE_SIZE 1 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_RESERVED_LSB 6 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_RESERVED_MASK 0xC0 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_RESERVED_MSB 7 |
| #define SI446X_PROP_PKT_RX_FIELD_5_CRC_CONFIG_RESERVED_SIZE 2 |
| #define SI446X_PROP_PKT_RX_FIELD_5_LENGTH_12_8_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_5_LENGTH_12_8_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_5_LENGTH_12_8_RX_FIELD_5_LENGTH_12_8_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_5_LENGTH_12_8_RX_FIELD_5_LENGTH_12_8_MASK 0x1F |
| #define SI446X_PROP_PKT_RX_FIELD_5_LENGTH_12_8_RX_FIELD_5_LENGTH_12_8_MSB 4 |
| #define SI446X_PROP_PKT_RX_FIELD_5_LENGTH_12_8_RX_FIELD_5_LENGTH_12_8_SIZE 5 |
| #define SI446X_PROP_PKT_RX_FIELD_5_LENGTH_7_0_DEFAULT 0x00 |
| #define SI446X_PROP_PKT_RX_FIELD_5_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_5_LENGTH_7_0_RX_FIELD_5_LENGTH_7_0_LSB 0 |
| #define SI446X_PROP_PKT_RX_FIELD_5_LENGTH_7_0_RX_FIELD_5_LENGTH_7_0_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_FIELD_5_LENGTH_7_0_RX_FIELD_5_LENGTH_7_0_MAX 0xff |
| #define SI446X_PROP_PKT_RX_FIELD_5_LENGTH_7_0_RX_FIELD_5_LENGTH_7_0_MIN 0 |
| #define SI446X_PROP_PKT_RX_FIELD_5_LENGTH_7_0_RX_FIELD_5_LENGTH_7_0_MSB 7 |
| #define SI446X_PROP_PKT_RX_FIELD_5_LENGTH_7_0_RX_FIELD_5_LENGTH_7_0_SIZE 8 |
| #define SI446X_PROP_PKT_RX_THRESHOLD_DEFAULT 0x30 |
| #define SI446X_PROP_PKT_RX_THRESHOLD_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_THRESHOLD_RX_THRESHOLD_LSB 0 |
| #define SI446X_PROP_PKT_RX_THRESHOLD_RX_THRESHOLD_MASK 0xFF |
| #define SI446X_PROP_PKT_RX_THRESHOLD_RX_THRESHOLD_MAX 64 |
| #define SI446X_PROP_PKT_RX_THRESHOLD_RX_THRESHOLD_MIN 0 |
| #define SI446X_PROP_PKT_RX_THRESHOLD_RX_THRESHOLD_MSB 7 |
| #define SI446X_PROP_PKT_RX_THRESHOLD_RX_THRESHOLD_SIZE 8 |
| #define SI446X_PROP_PKT_TX_THRESHOLD_DEFAULT 0x30 |
| #define SI446X_PROP_PKT_TX_THRESHOLD_MASK 0xFF |
| #define SI446X_PROP_PKT_TX_THRESHOLD_TX_THRESHOLD_LSB 0 |
| #define SI446X_PROP_PKT_TX_THRESHOLD_TX_THRESHOLD_MASK 0xFF |
| #define SI446X_PROP_PKT_TX_THRESHOLD_TX_THRESHOLD_MAX 64 |
| #define SI446X_PROP_PKT_TX_THRESHOLD_TX_THRESHOLD_MIN 0 |
| #define SI446X_PROP_PKT_TX_THRESHOLD_TX_THRESHOLD_MSB 7 |
| #define SI446X_PROP_PKT_TX_THRESHOLD_TX_THRESHOLD_SIZE 8 |
| #define SI446X_PROP_PREAMBLE_CONFIG_DEFAULT 0x21 |
| #define SI446X_PROP_PREAMBLE_CONFIG_LENGTH_CONFIG_BIT 0x10 |
| #define SI446X_PROP_PREAMBLE_CONFIG_LENGTH_CONFIG_ENUM_BYTE 0x1 |
| #define SI446X_PROP_PREAMBLE_CONFIG_LENGTH_CONFIG_ENUM_NIBBLE 0x0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_LENGTH_CONFIG_LSB 4 |
| #define SI446X_PROP_PREAMBLE_CONFIG_LENGTH_CONFIG_MASK 0x10 |
| #define SI446X_PROP_PREAMBLE_CONFIG_LENGTH_CONFIG_MSB 4 |
| #define SI446X_PROP_PREAMBLE_CONFIG_LENGTH_CONFIG_SIZE 1 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MAN_CONST_BIT 0x8 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MAN_CONST_ENUM_CONST 0x1 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MAN_CONST_ENUM_NO_CON 0x0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MAN_CONST_LSB 3 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MAN_CONST_MASK 0x8 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MAN_CONST_MSB 3 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MAN_CONST_SIZE 1 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MAN_ENABLE_BIT 0x4 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MAN_ENABLE_ENUM_EN_MAN 0x1 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MAN_ENABLE_ENUM_NO_MAN 0x0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MAN_ENABLE_LSB 2 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MAN_ENABLE_MASK 0x4 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MAN_ENABLE_MSB 2 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MAN_ENABLE_SIZE 1 |
| #define SI446X_PROP_PREAMBLE_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_CONFIG_NSTD_DEFAULT 0x00 |
| #define SI446X_PROP_PREAMBLE_CONFIG_NSTD_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_CONFIG_NSTD_PATTERN_LENGTH_LSB 0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_NSTD_PATTERN_LENGTH_MASK 0x1F |
| #define SI446X_PROP_PREAMBLE_CONFIG_NSTD_PATTERN_LENGTH_MAX 31 |
| #define SI446X_PROP_PREAMBLE_CONFIG_NSTD_PATTERN_LENGTH_MIN 0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_NSTD_PATTERN_LENGTH_MSB 4 |
| #define SI446X_PROP_PREAMBLE_CONFIG_NSTD_PATTERN_LENGTH_SIZE 5 |
| #define SI446X_PROP_PREAMBLE_CONFIG_NSTD_RX_ERRORS_LSB 5 |
| #define SI446X_PROP_PREAMBLE_CONFIG_NSTD_RX_ERRORS_MASK 0xE0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_NSTD_RX_ERRORS_MAX 7 |
| #define SI446X_PROP_PREAMBLE_CONFIG_NSTD_RX_ERRORS_MIN 0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_NSTD_RX_ERRORS_MSB 7 |
| #define SI446X_PROP_PREAMBLE_CONFIG_NSTD_RX_ERRORS_SIZE 3 |
| #define SI446X_PROP_PREAMBLE_CONFIG_PREAM_FIRST_1_OR_0_BIT 0x20 |
| #define SI446X_PROP_PREAMBLE_CONFIG_PREAM_FIRST_1_OR_0_ENUM_FIRST_0 0x0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_PREAM_FIRST_1_OR_0_ENUM_FIRST_1 0x1 |
| #define SI446X_PROP_PREAMBLE_CONFIG_PREAM_FIRST_1_OR_0_LSB 5 |
| #define SI446X_PROP_PREAMBLE_CONFIG_PREAM_FIRST_1_OR_0_MASK 0x20 |
| #define SI446X_PROP_PREAMBLE_CONFIG_PREAM_FIRST_1_OR_0_MSB 5 |
| #define SI446X_PROP_PREAMBLE_CONFIG_PREAM_FIRST_1_OR_0_SIZE 1 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STANDARD_PREAM_ENUM_PRE_0101 0x2 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STANDARD_PREAM_ENUM_PRE_1010 0x1 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STANDARD_PREAM_ENUM_PRE_NS 0x0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STANDARD_PREAM_LSB 0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STANDARD_PREAM_MASK 0x3 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STANDARD_PREAM_MSB 1 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STANDARD_PREAM_SIZE 2 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_1_DEFAULT 0x14 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_1_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_1_RX_THRESH_LSB 0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_1_RX_THRESH_MASK 0x7F |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_1_RX_THRESH_MAX 127 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_1_RX_THRESH_MIN 0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_1_RX_THRESH_MSB 6 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_1_RX_THRESH_SIZE 7 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_1_SKIP_SYNC_TIMEOUT_BIT 0x80 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_1_SKIP_SYNC_TIMEOUT_ENUM_ENABLE 0x1 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_1_SKIP_SYNC_TIMEOUT_LSB 7 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_1_SKIP_SYNC_TIMEOUT_MASK 0x80 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_1_SKIP_SYNC_TIMEOUT_MSB 7 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_1_SKIP_SYNC_TIMEOUT_SIZE 1 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_2_DEFAULT 0x0F |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_2_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_2_RX_PREAMBLE_TIMEOUT_EXTEND_LSB 4 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_2_RX_PREAMBLE_TIMEOUT_EXTEND_MASK 0xF0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_2_RX_PREAMBLE_TIMEOUT_EXTEND_MAX 15 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_2_RX_PREAMBLE_TIMEOUT_EXTEND_MIN 0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_2_RX_PREAMBLE_TIMEOUT_EXTEND_MSB 7 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_2_RX_PREAMBLE_TIMEOUT_EXTEND_SIZE 4 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_2_RX_PREAMBLE_TIMEOUT_LSB 0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_2_RX_PREAMBLE_TIMEOUT_MASK 0xF |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_2_RX_PREAMBLE_TIMEOUT_MAX 15 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_2_RX_PREAMBLE_TIMEOUT_MIN 0 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_2_RX_PREAMBLE_TIMEOUT_MSB 3 |
| #define SI446X_PROP_PREAMBLE_CONFIG_STD_2_RX_PREAMBLE_TIMEOUT_SIZE 4 |
| #define SI446X_PROP_PREAMBLE_PATTERN_15_8_DEFAULT 0 |
| #define SI446X_PROP_PREAMBLE_PATTERN_15_8_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_PATTERN_15_8_PATTERN_15_8_LSB 0 |
| #define SI446X_PROP_PREAMBLE_PATTERN_15_8_PATTERN_15_8_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_PATTERN_15_8_PATTERN_15_8_MAX 0xff |
| #define SI446X_PROP_PREAMBLE_PATTERN_15_8_PATTERN_15_8_MIN 0 |
| #define SI446X_PROP_PREAMBLE_PATTERN_15_8_PATTERN_15_8_MSB 7 |
| #define SI446X_PROP_PREAMBLE_PATTERN_15_8_PATTERN_15_8_SIZE 8 |
| #define SI446X_PROP_PREAMBLE_PATTERN_23_16_DEFAULT 0 |
| #define SI446X_PROP_PREAMBLE_PATTERN_23_16_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_PATTERN_23_16_PATTERN_23_16_LSB 0 |
| #define SI446X_PROP_PREAMBLE_PATTERN_23_16_PATTERN_23_16_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_PATTERN_23_16_PATTERN_23_16_MAX 0xff |
| #define SI446X_PROP_PREAMBLE_PATTERN_23_16_PATTERN_23_16_MIN 0 |
| #define SI446X_PROP_PREAMBLE_PATTERN_23_16_PATTERN_23_16_MSB 7 |
| #define SI446X_PROP_PREAMBLE_PATTERN_23_16_PATTERN_23_16_SIZE 8 |
| #define SI446X_PROP_PREAMBLE_PATTERN_31_24_DEFAULT 0 |
| #define SI446X_PROP_PREAMBLE_PATTERN_31_24_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_PATTERN_31_24_PATTERN_31_24_LSB 0 |
| #define SI446X_PROP_PREAMBLE_PATTERN_31_24_PATTERN_31_24_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_PATTERN_31_24_PATTERN_31_24_MAX 0xff |
| #define SI446X_PROP_PREAMBLE_PATTERN_31_24_PATTERN_31_24_MIN 0 |
| #define SI446X_PROP_PREAMBLE_PATTERN_31_24_PATTERN_31_24_MSB 7 |
| #define SI446X_PROP_PREAMBLE_PATTERN_31_24_PATTERN_31_24_SIZE 8 |
| #define SI446X_PROP_PREAMBLE_PATTERN_7_0_DEFAULT 0 |
| #define SI446X_PROP_PREAMBLE_PATTERN_7_0_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_PATTERN_7_0_PATTERN_7_0_LSB 0 |
| #define SI446X_PROP_PREAMBLE_PATTERN_7_0_PATTERN_7_0_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_PATTERN_7_0_PATTERN_7_0_MAX 0xff |
| #define SI446X_PROP_PREAMBLE_PATTERN_7_0_PATTERN_7_0_MIN 0 |
| #define SI446X_PROP_PREAMBLE_PATTERN_7_0_PATTERN_7_0_MSB 7 |
| #define SI446X_PROP_PREAMBLE_PATTERN_7_0_PATTERN_7_0_SIZE 8 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_DEFAULT 0x00 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_PKT_VALID_ON_POSTAMBLE_BIT 0x40 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_PKT_VALID_ON_POSTAMBLE_ENUM_FALSE 0x0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_PKT_VALID_ON_POSTAMBLE_ENUM_TRUE 0x1 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_PKT_VALID_ON_POSTAMBLE_LSB 6 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_PKT_VALID_ON_POSTAMBLE_MASK 0x40 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_PKT_VALID_ON_POSTAMBLE_MSB 6 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_PKT_VALID_ON_POSTAMBLE_SIZE 1 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_POSTAMBLE_ENABLE_BIT 0x80 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_POSTAMBLE_ENABLE_ENUM_FALSE 0x0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_POSTAMBLE_ENABLE_ENUM_TRUE 0x1 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_POSTAMBLE_ENABLE_LSB 7 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_POSTAMBLE_ENABLE_MASK 0x80 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_POSTAMBLE_ENABLE_MSB 7 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_POSTAMBLE_ENABLE_SIZE 1 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_POSTAMBLE_SIZE_LSB 0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_POSTAMBLE_SIZE_MASK 0x3 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_POSTAMBLE_SIZE_MSB 1 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_CONFIG_POSTAMBLE_SIZE_SIZE 2 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_15_8_DEFAULT 0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_15_8_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_15_8_POSTAMBLE_PATTERN_15_8_LSB 0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_15_8_POSTAMBLE_PATTERN_15_8_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_15_8_POSTAMBLE_PATTERN_15_8_MAX 0xff |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_15_8_POSTAMBLE_PATTERN_15_8_MIN 0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_15_8_POSTAMBLE_PATTERN_15_8_MSB 7 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_15_8_POSTAMBLE_PATTERN_15_8_SIZE 8 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_23_16_DEFAULT 0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_23_16_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_23_16_POSTAMBLE_PATTERN_23_16_LSB 0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_23_16_POSTAMBLE_PATTERN_23_16_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_23_16_POSTAMBLE_PATTERN_23_16_MAX 0xff |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_23_16_POSTAMBLE_PATTERN_23_16_MIN 0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_23_16_POSTAMBLE_PATTERN_23_16_MSB 7 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_23_16_POSTAMBLE_PATTERN_23_16_SIZE 8 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_31_24_DEFAULT 0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_31_24_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_31_24_POSTAMBLE_PATTERN_31_24_LSB 0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_31_24_POSTAMBLE_PATTERN_31_24_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_31_24_POSTAMBLE_PATTERN_31_24_MAX 0xff |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_31_24_POSTAMBLE_PATTERN_31_24_MIN 0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_31_24_POSTAMBLE_PATTERN_31_24_MSB 7 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_31_24_POSTAMBLE_PATTERN_31_24_SIZE 8 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_7_0_DEFAULT 0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_7_0_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_7_0_POSTAMBLE_PATTERN_7_0_LSB 0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_7_0_POSTAMBLE_PATTERN_7_0_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_7_0_POSTAMBLE_PATTERN_7_0_MAX 0xff |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_7_0_POSTAMBLE_PATTERN_7_0_MIN 0 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_7_0_POSTAMBLE_PATTERN_7_0_MSB 7 |
| #define SI446X_PROP_PREAMBLE_POSTAMBLE_PATTERN_7_0_POSTAMBLE_PATTERN_7_0_SIZE 8 |
| #define SI446X_PROP_PREAMBLE_TX_LENGTH_DEFAULT 0x08 |
| #define SI446X_PROP_PREAMBLE_TX_LENGTH_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_TX_LENGTH_TX_LENGTH_LSB 0 |
| #define SI446X_PROP_PREAMBLE_TX_LENGTH_TX_LENGTH_MASK 0xFF |
| #define SI446X_PROP_PREAMBLE_TX_LENGTH_TX_LENGTH_MAX 255 |
| #define SI446X_PROP_PREAMBLE_TX_LENGTH_TX_LENGTH_MIN 0 |
| #define SI446X_PROP_PREAMBLE_TX_LENGTH_TX_LENGTH_MSB 7 |
| #define SI446X_PROP_PREAMBLE_TX_LENGTH_TX_LENGTH_SIZE 8 |
| #define SI446X_PROP_RX_HOP_CONTROL_DEFAULT 0x04 |
| #define SI446X_PROP_RX_HOP_CONTROL_HOP_EN_ENUM_HOP_DISABLE 0 |
| #define SI446X_PROP_RX_HOP_CONTROL_HOP_EN_ENUM_HOP_PM_SYNC_TO 3 |
| #define SI446X_PROP_RX_HOP_CONTROL_HOP_EN_ENUM_HOP_PM_TO 1 |
| #define SI446X_PROP_RX_HOP_CONTROL_HOP_EN_ENUM_HOP_RSSI_PM_SYNC_TO 4 |
| #define SI446X_PROP_RX_HOP_CONTROL_HOP_EN_ENUM_HOP_RSSI_PM_TO 2 |
| #define SI446X_PROP_RX_HOP_CONTROL_HOP_EN_LSB 4 |
| #define SI446X_PROP_RX_HOP_CONTROL_HOP_EN_MASK 0x70 |
| #define SI446X_PROP_RX_HOP_CONTROL_HOP_EN_MSB 6 |
| #define SI446X_PROP_RX_HOP_CONTROL_HOP_EN_SIZE 3 |
| #define SI446X_PROP_RX_HOP_CONTROL_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_CONTROL_RSSI_TIMEOUT_LSB 0 |
| #define SI446X_PROP_RX_HOP_CONTROL_RSSI_TIMEOUT_MASK 0xF |
| #define SI446X_PROP_RX_HOP_CONTROL_RSSI_TIMEOUT_MSB 3 |
| #define SI446X_PROP_RX_HOP_CONTROL_RSSI_TIMEOUT_SIZE 4 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_0_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_0_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_0_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_0_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_0_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_0_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_0_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_0_DEFAULT 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_0_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_10_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_10_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_10_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_10_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_10_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_10_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_10_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_10_DEFAULT 10 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_10_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_11_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_11_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_11_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_11_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_11_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_11_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_11_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_11_DEFAULT 11 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_11_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_12_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_12_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_12_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_12_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_12_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_12_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_12_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_12_DEFAULT 12 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_12_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_13_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_13_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_13_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_13_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_13_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_13_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_13_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_13_DEFAULT 13 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_13_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_14_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_14_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_14_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_14_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_14_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_14_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_14_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_14_DEFAULT 14 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_14_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_15_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_15_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_15_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_15_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_15_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_15_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_15_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_15_DEFAULT 15 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_15_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_16_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_16_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_16_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_16_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_16_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_16_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_16_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_16_DEFAULT 16 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_16_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_17_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_17_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_17_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_17_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_17_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_17_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_17_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_17_DEFAULT 17 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_17_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_18_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_18_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_18_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_18_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_18_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_18_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_18_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_18_DEFAULT 18 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_18_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_19_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_19_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_19_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_19_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_19_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_19_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_19_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_19_DEFAULT 19 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_19_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_1_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_1_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_1_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_1_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_1_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_1_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_1_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_1_DEFAULT 1 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_1_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_20_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_20_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_20_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_20_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_20_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_20_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_20_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_20_DEFAULT 20 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_20_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_21_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_21_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_21_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_21_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_21_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_21_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_21_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_21_DEFAULT 21 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_21_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_22_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_22_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_22_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_22_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_22_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_22_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_22_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_22_DEFAULT 22 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_22_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_23_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_23_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_23_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_23_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_23_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_23_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_23_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_23_DEFAULT 23 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_23_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_24_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_24_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_24_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_24_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_24_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_24_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_24_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_24_DEFAULT 24 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_24_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_25_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_25_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_25_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_25_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_25_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_25_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_25_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_25_DEFAULT 25 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_25_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_26_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_26_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_26_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_26_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_26_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_26_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_26_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_26_DEFAULT 26 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_26_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_27_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_27_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_27_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_27_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_27_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_27_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_27_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_27_DEFAULT 27 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_27_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_28_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_28_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_28_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_28_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_28_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_28_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_28_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_28_DEFAULT 28 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_28_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_29_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_29_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_29_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_29_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_29_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_29_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_29_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_29_DEFAULT 29 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_29_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_2_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_2_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_2_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_2_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_2_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_2_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_2_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_2_DEFAULT 2 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_2_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_30_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_30_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_30_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_30_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_30_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_30_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_30_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_30_DEFAULT 30 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_30_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_31_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_31_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_31_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_31_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_31_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_31_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_31_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_31_DEFAULT 31 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_31_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_32_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_32_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_32_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_32_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_32_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_32_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_32_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_32_DEFAULT 32 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_32_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_33_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_33_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_33_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_33_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_33_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_33_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_33_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_33_DEFAULT 33 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_33_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_34_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_34_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_34_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_34_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_34_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_34_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_34_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_34_DEFAULT 34 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_34_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_35_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_35_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_35_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_35_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_35_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_35_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_35_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_35_DEFAULT 35 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_35_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_36_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_36_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_36_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_36_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_36_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_36_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_36_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_36_DEFAULT 36 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_36_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_37_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_37_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_37_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_37_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_37_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_37_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_37_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_37_DEFAULT 37 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_37_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_38_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_38_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_38_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_38_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_38_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_38_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_38_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_38_DEFAULT 38 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_38_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_39_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_39_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_39_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_39_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_39_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_39_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_39_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_39_DEFAULT 39 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_39_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_3_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_3_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_3_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_3_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_3_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_3_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_3_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_3_DEFAULT 3 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_3_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_40_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_40_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_40_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_40_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_40_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_40_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_40_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_40_DEFAULT 40 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_40_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_41_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_41_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_41_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_41_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_41_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_41_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_41_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_41_DEFAULT 41 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_41_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_42_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_42_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_42_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_42_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_42_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_42_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_42_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_42_DEFAULT 42 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_42_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_43_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_43_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_43_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_43_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_43_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_43_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_43_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_43_DEFAULT 43 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_43_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_44_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_44_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_44_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_44_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_44_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_44_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_44_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_44_DEFAULT 44 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_44_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_45_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_45_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_45_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_45_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_45_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_45_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_45_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_45_DEFAULT 45 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_45_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_46_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_46_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_46_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_46_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_46_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_46_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_46_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_46_DEFAULT 46 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_46_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_47_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_47_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_47_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_47_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_47_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_47_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_47_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_47_DEFAULT 47 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_47_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_48_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_48_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_48_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_48_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_48_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_48_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_48_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_48_DEFAULT 48 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_48_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_49_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_49_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_49_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_49_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_49_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_49_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_49_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_49_DEFAULT 49 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_49_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_4_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_4_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_4_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_4_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_4_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_4_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_4_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_4_DEFAULT 4 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_4_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_50_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_50_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_50_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_50_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_50_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_50_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_50_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_50_DEFAULT 50 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_50_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_51_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_51_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_51_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_51_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_51_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_51_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_51_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_51_DEFAULT 51 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_51_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_52_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_52_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_52_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_52_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_52_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_52_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_52_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_52_DEFAULT 52 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_52_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_53_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_53_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_53_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_53_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_53_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_53_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_53_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_53_DEFAULT 53 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_53_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_54_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_54_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_54_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_54_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_54_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_54_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_54_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_54_DEFAULT 54 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_54_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_55_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_55_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_55_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_55_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_55_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_55_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_55_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_55_DEFAULT 55 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_55_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_56_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_56_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_56_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_56_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_56_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_56_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_56_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_56_DEFAULT 56 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_56_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_57_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_57_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_57_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_57_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_57_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_57_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_57_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_57_DEFAULT 57 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_57_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_58_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_58_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_58_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_58_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_58_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_58_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_58_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_58_DEFAULT 58 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_58_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_59_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_59_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_59_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_59_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_59_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_59_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_59_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_59_DEFAULT 59 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_59_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_5_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_5_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_5_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_5_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_5_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_5_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_5_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_5_DEFAULT 5 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_5_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_60_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_60_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_60_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_60_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_60_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_60_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_60_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_60_DEFAULT 60 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_60_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_61_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_61_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_61_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_61_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_61_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_61_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_61_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_61_DEFAULT 61 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_61_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_62_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_62_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_62_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_62_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_62_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_62_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_62_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_62_DEFAULT 62 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_62_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_63_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_63_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_63_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_63_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_63_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_63_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_63_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_63_DEFAULT 63 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_63_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_6_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_6_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_6_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_6_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_6_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_6_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_6_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_6_DEFAULT 6 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_6_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_7_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_7_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_7_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_7_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_7_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_7_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_7_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_7_DEFAULT 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_7_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_8_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_8_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_8_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_8_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_8_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_8_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_8_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_8_DEFAULT 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_8_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_9_CHANNEL_NUM_ENUM_INVALID 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_9_CHANNEL_NUM_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_9_CHANNEL_NUM_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_9_CHANNEL_NUM_MAX 255 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_9_CHANNEL_NUM_MIN 0 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_9_CHANNEL_NUM_MSB 7 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_9_CHANNEL_NUM_SIZE 8 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_9_DEFAULT 9 |
| #define SI446X_PROP_RX_HOP_TABLE_ENTRY_9_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_SIZE_DEFAULT 0x01 |
| #define SI446X_PROP_RX_HOP_TABLE_SIZE_MASK 0xFF |
| #define SI446X_PROP_RX_HOP_TABLE_SIZE_RX_HOP_TABLE_SIZE_LSB 0 |
| #define SI446X_PROP_RX_HOP_TABLE_SIZE_RX_HOP_TABLE_SIZE_MASK 0x7F |
| #define SI446X_PROP_RX_HOP_TABLE_SIZE_RX_HOP_TABLE_SIZE_MAX 64 |
| #define SI446X_PROP_RX_HOP_TABLE_SIZE_RX_HOP_TABLE_SIZE_MIN 1 |
| #define SI446X_PROP_RX_HOP_TABLE_SIZE_RX_HOP_TABLE_SIZE_MSB 6 |
| #define SI446X_PROP_RX_HOP_TABLE_SIZE_RX_HOP_TABLE_SIZE_SIZE 7 |
| #define SI446X_PROP_SYNC_BITS_15_8_BITS_15_8_LSB 0 |
| #define SI446X_PROP_SYNC_BITS_15_8_BITS_15_8_MASK 0xFF |
| #define SI446X_PROP_SYNC_BITS_15_8_BITS_15_8_MAX 0xff |
| #define SI446X_PROP_SYNC_BITS_15_8_BITS_15_8_MIN 0 |
| #define SI446X_PROP_SYNC_BITS_15_8_BITS_15_8_MSB 7 |
| #define SI446X_PROP_SYNC_BITS_15_8_BITS_15_8_SIZE 8 |
| #define SI446X_PROP_SYNC_BITS_15_8_DEFAULT 0x2D |
| #define SI446X_PROP_SYNC_BITS_15_8_MASK 0xFF |
| #define SI446X_PROP_SYNC_BITS_23_16_BITS_23_16_LSB 0 |
| #define SI446X_PROP_SYNC_BITS_23_16_BITS_23_16_MASK 0xFF |
| #define SI446X_PROP_SYNC_BITS_23_16_BITS_23_16_MAX 0xff |
| #define SI446X_PROP_SYNC_BITS_23_16_BITS_23_16_MIN 0 |
| #define SI446X_PROP_SYNC_BITS_23_16_BITS_23_16_MSB 7 |
| #define SI446X_PROP_SYNC_BITS_23_16_BITS_23_16_SIZE 8 |
| #define SI446X_PROP_SYNC_BITS_23_16_DEFAULT 0xD4 |
| #define SI446X_PROP_SYNC_BITS_23_16_MASK 0xFF |
| #define SI446X_PROP_SYNC_BITS_31_24_BITS_31_24_LSB 0 |
| #define SI446X_PROP_SYNC_BITS_31_24_BITS_31_24_MASK 0xFF |
| #define SI446X_PROP_SYNC_BITS_31_24_BITS_31_24_MAX 0xff |
| #define SI446X_PROP_SYNC_BITS_31_24_BITS_31_24_MIN 0 |
| #define SI446X_PROP_SYNC_BITS_31_24_BITS_31_24_MSB 7 |
| #define SI446X_PROP_SYNC_BITS_31_24_BITS_31_24_SIZE 8 |
| #define SI446X_PROP_SYNC_BITS_31_24_DEFAULT 0x2D |
| #define SI446X_PROP_SYNC_BITS_31_24_MASK 0xFF |
| #define SI446X_PROP_SYNC_BITS_7_0_BITS_7_0_LSB 0 |
| #define SI446X_PROP_SYNC_BITS_7_0_BITS_7_0_MASK 0xFF |
| #define SI446X_PROP_SYNC_BITS_7_0_BITS_7_0_MAX 0xff |
| #define SI446X_PROP_SYNC_BITS_7_0_BITS_7_0_MIN 0 |
| #define SI446X_PROP_SYNC_BITS_7_0_BITS_7_0_MSB 7 |
| #define SI446X_PROP_SYNC_BITS_7_0_BITS_7_0_SIZE 8 |
| #define SI446X_PROP_SYNC_BITS_7_0_DEFAULT 0xD4 |
| #define SI446X_PROP_SYNC_BITS_7_0_MASK 0xFF |
| #define SI446X_PROP_SYNC_CONFIG_4FSK_BIT 0x8 |
| #define SI446X_PROP_SYNC_CONFIG_4FSK_LSB 3 |
| #define SI446X_PROP_SYNC_CONFIG_4FSK_MASK 0x8 |
| #define SI446X_PROP_SYNC_CONFIG_4FSK_MSB 3 |
| #define SI446X_PROP_SYNC_CONFIG_4FSK_SIZE 1 |
| #define SI446X_PROP_SYNC_CONFIG_DEFAULT 0x01 |
| #define SI446X_PROP_SYNC_CONFIG_LENGTH_LSB 0 |
| #define SI446X_PROP_SYNC_CONFIG_LENGTH_MASK 0x3 |
| #define SI446X_PROP_SYNC_CONFIG_LENGTH_MSB 1 |
| #define SI446X_PROP_SYNC_CONFIG_LENGTH_SIZE 2 |
| #define SI446X_PROP_SYNC_CONFIG_MANCH_BIT 0x4 |
| #define SI446X_PROP_SYNC_CONFIG_MANCH_LSB 2 |
| #define SI446X_PROP_SYNC_CONFIG_MANCH_MASK 0x4 |
| #define SI446X_PROP_SYNC_CONFIG_MANCH_MSB 2 |
| #define SI446X_PROP_SYNC_CONFIG_MANCH_SIZE 1 |
| #define SI446X_PROP_SYNC_CONFIG_MASK 0xFF |
| #define SI446X_PROP_SYNC_CONFIG_RX_ERRORS_LSB 4 |
| #define SI446X_PROP_SYNC_CONFIG_RX_ERRORS_MASK 0x70 |
| #define SI446X_PROP_SYNC_CONFIG_RX_ERRORS_MSB 6 |
| #define SI446X_PROP_SYNC_CONFIG_RX_ERRORS_SIZE 3 |
| #define SI446X_PROP_SYNC_CONFIG_SKIP_TX_BIT 0x80 |
| #define SI446X_PROP_SYNC_CONFIG_SKIP_TX_LSB 7 |
| #define SI446X_PROP_SYNC_CONFIG_SKIP_TX_MASK 0x80 |
| #define SI446X_PROP_SYNC_CONFIG_SKIP_TX_MSB 7 |
| #define SI446X_PROP_SYNC_CONFIG_SKIP_TX_SIZE 1 |
| typedef int16_t S16 |
| typedef uint32_t S32 |
| typedef int8_t S8 |
| typedef uint16_t U16 |
| typedef uint32_t U32 |
| typedef uint8_t U8 |
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